Coded data generation or conversion – Analog to or from digital conversion – Nonlinear
Reexamination Certificate
2000-01-27
2002-09-03
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Nonlinear
C341S143000, C341S155000
Reexamination Certificate
active
06445320
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an A/D conversion apparatus that carries out delta-sigma (&Dgr;&Sgr;) A/D conversion through oversampling, and more particularly to an AD conversion apparatus of this kind that suitably carries out the A/D conversion over a wide dynamic range through control of the input gain.
2. Prior Art
A/D converters are used for conversion of an analog signal to a digital signal, and some of them employ a so-called floating method to enhance the accuracy of A/D conversion. An A/D converter employing the floating method controls the gain of an input analog signal according to a digital signal after the A/D conversion.
FIG. 1
shows a conventional A/D conversion system based on the floating method.
In the figure, reference numeral
100
designates an input gain control circuit to which an input analog signal Sin is supplied. The input gain control circuit
100
controls the input gain based on a control signal C. Reference numeral
200
designates an A/D converter connected to the input gain control circuit
100
. The A/D converter
200
converts an analog signal output from the circuit
100
to a digital signal. Reference numeral
300
designates a CPU provided at the next stage of the A/D converter
200
. The CPU
300
loads a control program into a main memory for working, and generates the control signal C by executing the program such that the digital signal assumes values within a predetermined range.
The A/D conversion system constructed as above operates in the following manner: When the level of the input analog signal Sin becomes higher than a predetermined value, the CPU
300
detects this and generates the control signal C such that the input gain is decreased. On the other hand, when the level of the input analog signal Sin becomes lower than the predetermined value, the CPU
300
detects this and generates the control signal C such that the input gain is increased. In this way, the input gain is adjusted such that the level of the input signal to the A/D converter
200
is maintained within a predetermined appropriate range. For instance, where the input gain is switched between four stages, it is possible to realize an A/D converter with 10 bit accuracy by using the A/D converter
200
with 8 bit accuracy.
The A/D conversion system described above generates the control signal C by executing the program by the CPU
300
to maintain the level of input signal to the A/D converter
200
within the predetermined appropriate range. This brings about the following problems:
First, it is required to provide the CPU
300
and a storage device to store the program, and this complicates the construction of the system.
Secondly, since the CPU
300
carries out an arithmetic operation, it takes time to generate the control signal C, resulting in a poor response of the system. For instance, when the input analog signal rises sharply, if the arithmetic operation is not carried out fast enough, the control signal cannot be generated in a manner fully following up a change in the input analog signal, so that the waveform of the signal can be clipped.
Thirdly, if the number of bits of the output of the A/D converter
200
is increased, load on the CPU
300
is increased due to an increase in the required arithmetic operation.
On the other hand, another type of A/D conversion apparatus, which is based on the &Dgr;&Sgr; method, is conventionally known.
FIG. 2
shows the construction of the conventional A/D conversion apparatus based on the &Dgr;&Sgr; method. A &Dgr;&Sgr; modulator
31
for converting an input analog signal into serial-bit strings is comprised of a switched-capacitor integrator
33
, a one-bit quantizer
33
formed by a clocked comparator for quantizing an output of the integrator
33
, and a feedback circuit
34
for feeding back an output of the one-bit quantizer
33
to the integrator
32
, by delaying the output by one sample based on a positive reference voltage VREF+ or a negative reference voltage VREF− selected depending upon the polarity of the output. The serial bit strings obtained by the &Dgr;&Sgr; modulator
31
are delivered to a digital filter
35
where low-frequency components corresponding to the input analog signal are extracted and converted into digital data having a predetermined number of bits.
To reduce noise of an output digital signal from the A/D conversion apparatus constructed as above, there has been proposed by U.S. Pat. No. 4,851,841 a scaling method which reduces the gain of the &Dgr;&Sgr; modulator
31
to 1/A (=1/1.25, for example), and designs the digital filter
35
to have impulse-response coefficients which are selected to provide a gain of A (=1.25, for example).
If the analog input signal contains a DC offset component, to remove the DC offset component at last, it is required that the digital filter
35
is followed by a high-pass filter
36
, for example, as shown in FIG.
3
. However, when providing the high-pass filter which follows the digital filter
35
under a condition where a certain gain is applied to the digital filter by employing the aforementioned scaling system, the DC offset component can be removed, but a positive or negative part of the input analog signal (actually the digital signal) can be clipped for high-level signals. Such a clipped state may cause deformation corresponding to overflow of data.
To solve this problem, the present assignee has proposed, by U.S. Pat. No. 5,757,299, a scaling method which multiplies the output of the high-pass filter which removes the DC offset component by a factor of A to compensate for the reduction of the gain of the &Dgr;&Sgr; modulator to 1/A, thereby effectively reducing noise while eliminating effect due to occurrence of a clipped state in the analog input signal.
SUMMARY OF THE INVENTION
It is a first object of the invention to provide an A/D conversion apparatus which is capable of securing a wide dynamic range of A/D conversion with a simple construction through suitably switching the input gain of the input analog signal between predetermined levels.
A second object of the invention is to provide an A/D conversion apparatus which is capable of effectively reducing noise of the output digital signal while securing a wide dynamic range of A/D conversion.
To attain the first object, according to a first aspect of the invention, there is provided an A/D conversion apparatus comprising an input gain control device that controls gain of an input signal based on a control signal, a &Dgr;&Sgr; modulator converter that carries out oversampling of the input signal having the gain thereof controlled by the input gain control device to convert the input signal to data of one bit, a detecting device that detects a peak value of the input signal based on the data of one bit, and a gain control device that generates the control signal based on the peak value detected by the detecting device in a manner such that the input signal having the gain thereof controlled falls within a predetermined range.
To attain the first object, according to a second aspect of the invention, there is provided an A/D conversion apparatus comprising an input gain control device that controls gain of an input signal based on a control signal, a &Dgr;&Sgr; modulator that carries out oversampling of the input signal having the gain thereof controlled by the input gain control device to convert the input signal to data of one bit, a moving average-calculating device that calculates moving average data indicative of a moving average of the data of one bit, and a gain control device that generates the control signal based on the moving average data in a manner such that the input signal having the gain thereof controlled falls within a predetermined range.
Preferably, the moving average-calculating device calculates the moving average data based on a plurality of values of the data of one bit in a manner such that shaping noise generated by the oversampling of the input signal by the &Dgr;&Sgr; modulator can b
Kamiya Ryo
Noro Masao
Sogo Akira
Morrison & Foerster / LLP
Nguyen John
Yamaha Corporation
Young Brian
LandOfFree
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