7 to 3 counter circuit

Details 7 to 3 counter circuit 7 to 3 counter circuit

1991-05-17

1992-09-15

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

051483882

ABSTRACT:
A 7 to 3 counter adds seven digital inputs all having a weight X and provides a three-bit sum including a sum bit having a weight X, a first carry bit having a weight 2X and a second carry bit having a weight 4X. The counter includes seven inputs arranged in consecutive order for receiving a binary 1 or a binary 0 input signal level at each of the inputs. A first circuit means is coupled to all of the inputs and provides the sum bit responsive to the binary levels of the inputs. Second, third, and fourth circuit means provides first, second and third intermediate carry bits. A full adder includes a first carry output and a second carry output and provides the first carry bit at the first carry output and the second carry bit at the second carry output responsive to the binary levels of the first, second, and third intermediate carry bits.

REFERENCES:
patent: 3535502 (1967-11-01), Clapper
patent: 3603776 (1971-09-01), Weinberger
patent: 3636334 (1972-01-01), Svoboda
patent: 3711692 (1973-01-01), Batcher
patent: 3723715 (1973-03-01), Chen et al.
patent: 3741475 (1973-06-01), Hardy et al.
patent: 4399517 (1983-08-01), Niehaus et al.
patent: 4488253 (1984-12-01), Lerouge
patent: 4604723 (1986-08-01), Burrows

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