64B/66B Encoding data generation method and circuit

Details 64B/66B Encoding data generation method and circuit 64B/66B Encoding data generation method and circuit

2007-10-24

2008-12-09

Mai, Lam T (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from packed format

C341S050000

Reexamination Certificate

active

07463169

ABSTRACT:
In a more effective data generation method and circuit used for 64B/66B encoding, when packet data, and head and tail information of the data packet are received, write user data in which a head and tail identifying bytes are respectively added to a head and a tail of the packet data based on the head and tail information is associated with control data indicating positions of both of the identifying bytes to be written in a memory sequentially from a predetermined address of the memory. From the predetermined address, user data by 8 bytes and the control data corresponding to the user data are sequentially read to be provided to a 64B/66B encoding circuit. During a period in which the reading can not be made, idle bytes for 8n bytes (n≧1) and control data indicating the idle bytes, or maintenance user data of 8n bytes (n≧2) in which the head and tail identifying bytes are respectively added to a head and a tail of the maintenance information and control data indicating positions of both of the identifying bytes are provided to the 64B/66B encoding circuit.

REFERENCES:
patent: 5517660 (1996-05-01), Rosich
patent: 6967601 (2005-11-01), Bossen
patent: 7127645 (2006-10-01), Toyoda et al.
patent: 7183951 (2007-02-01), Bossen
patent: 2004-193817 (2004-07-01), None
patent: 2004-289567 (2004-10-01), None
patent: 2004-320580 (2004-11-01), None

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