5V tolerant corner clamp with keep off circuit

Details 5V tolerant corner clamp with keep off circuit 5V tolerant corner clamp with keep off circuit

2001-12-05

2003-09-16

Tso, Edward H. (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

Reexamination Certificate

active

06621679

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a corner clamp and, more particularly, to a 5V tolerant corner clamp with a keep off circuit.
2. Description of the Related Art
An electrostatic discharge (ESD) protection circuit is a circuit that protects the input/output transistors of a semiconductor chip from an ESD event. An ESD event typically occurs when the chip is exposed to static electricity, such as when the pins or solder bumps of the chip are touched by an ungrounded person handling the chip, or when the chip slides across another surface on its pins or solder bumps.
For example, an ungrounded person handling a semiconductor chip can place a static electric charge as high as 2000V on the chip. This voltage is more than sufficient to destructively break down the gate oxide of the input/output transistors of the chip.
FIG. 1
shows a schematic diagram that illustrates a prior-art ESD protection circuit
100
. As shown in
FIG. 1
, circuit
100
includes an ESD plus ring
110
and an ESD minus ring
112
that are formed around the periphery of a semiconductor die
114
. In addition, circuit
100
includes a power pad
120
, a ground pad
122
, and a number of input/output (I/O) pads
124
.
As further shown in
FIG. 1
, circuit
100
includes a plurality of upper diodes D
1
that are connected to ESD plus ring
110
and the pads
120
,
122
, and
124
so that each pad is connected to ESD plus ring
110
via a diode D
1
. In addition, a plurality of lower diodes D
2
are connected to ESD minus ring
112
and the pads
120
,
122
, and
124
so that each pad is connected to ESD minus ring
112
via a diode D
2
. Circuit
100
also includes four corner clamps
130
that are connected to ESD plus ring
110
and ESD minus ring
112
.
In operation, when an ESD event occurs, a first pad, such as pad A, is zapped positively with respect to a second pad, such as pad B. In this situation, a zap current I
ZAP
flows from the first pad through the adjacent diode D
1
to ESD plus ring
110
, and then on to corner clamps
130
.
Corner clamps
130
are voltage controlled switches that each provide a low impedance pathway from ESD positive ring
110
to ESD negative ring
112
when an ESD event is present, and a high impedance pathway between rings
110
and
112
when an ESD event is not present.
When the first pad is zapped, the corner clamps
130
(which are shown open, not closed, in
FIG. 1
) close and the zap current I
ZAP
flows through clamps
130
to ESD minus ring
112
. From ring
112
, the zap current I
ZAP
flows through a diode D
2
and on to the second pad.
FIG. 2
shows a schematic diagram that illustrates corner clamp
130
. As shown in
FIG. 2
, clamp
130
includes a RC timing circuit
210
, an inverter
212
, and a switching transistor M
1
. Timing circuit
210
, in turn, includes a resistor R that is connected to ESD plus ring
110
, and a capacitor C that is connected to resistor R and ESD minus ring
112
.
Inverter
212
includes a PMOS transistor M
2
and a NMOS transistor M
3
. Transistor M
2
has a source connected to ESD plus ring
110
, a gate connected to resistor R and capacitor C, and a drain. Transistor M
3
has a source connected to ESD minus ring
112
, a gate connected to resistor R and capacitor C, and a drain connected to the drain of transistor M
2
. Further, switching transistor M
1
has a source connected to ESD minus ring
112
, a gate connected to the drains of transistors M
2
and M
3
, and a drain connected to ESD plus ring
110
.
In operation, when an ESD event occurs and the zap current I
ZAP
flows onto ESD plus ring
110
, the voltage on ESD plus ring
110
spikes up dramatically. The voltage on the gates of transistors M
2
and M
3
also spikes up but, due to the presence of RC timing circuit
110
, the gate voltage lags the voltage on ESD plus ring
110
.
As a result, the gate-to-source voltage of transistor M
2
falls below the threshold voltage of transistor M
2
, thereby turning on transistor M
2
for as long as the gate voltage lags the voltage on ring
110
. When transistor M
2
turns on, transistor M
2
pulls up the voltage on the gate of transistor M
1
, thereby turning on transistor M
1
. When transistor M
1
is turned on, clamp
130
provides a low impedance pathway from ESD plus ring
110
to ESD minus ring
112
.
Once the packaged integrated circuit has been attached to a circuit board, power has been applied to the integrated circuit, and a steady state condition has been reached, a first voltage is present on both ESD plus ring
110
and the gates of transistors M
2
and M
3
. For example, when pad
120
is a 3.3V power pad, a first voltage of 2.6V is present on ESD plus ring
110
due to the diode drop of adjacent diode D
1
. In addition, a second voltage is present on ESD minus ring
112
. For example, since pad
122
is ground, a second voltage of 0.7V is present on ESD minus ring
112
due to the diode drop of adjacent diode D
2
.
Since the first voltage is present on the gates of transistors M
2
and M
3
, transistor M
2
is turned off and transistor M
3
is turned on. When turned on, transistor M
3
pulls down the voltage on the gate of transistor M
1
, thereby turning off transistor M
1
. When transistor M
1
is turned off, clamp
130
provides a high impedance pathway from ESD plus ring
110
to ESD minus ring
112
.
One problem with clamp
130
is that clamp
130
falsely triggers when used with a 5V tolerant circuit. A 5V tolerant circuit is a circuit that internally utilizes a voltage less than 5V, such as 3.3V, but receives 5V signals. For example, I/O pad C in
FIG. 1
can be driven by an external driver that outputs signals ranging from zero to 5V.
When 5V signals are driven onto a signal pad, such as pad C, the voltage on ESD plus ring
110
spikes up from 2.6V to 4.3V (a diode drop less than 5V). In addition, when a large number of pads are driven to 5V at the same time, such as when the 64 pads of a PCI bus are simultaneously driven high, the voltage on ESD plus ring
110
can spike up to 4.8V.
Due to the timing lag provided by RC timing circuit
210
, the spike in voltage, a delta of 1.7V to 2.2V, causes the gate-to-source voltage of transistor M
2
to again fall below the threshold voltage, thereby turning on transistor M
2
. When transistor M
2
turns on, transistor M
2
pulls up the voltage on the gate of transistor M
1
, thereby turning on transistor M
1
.
Since transistor M
1
turned on in response to a 5V signal rather than in response to an ESD event, clamp
130
was falsely triggered. Falsely triggering clamp
130
increases power dissipation and significantly loads the external device that is driving the signal pad.
Thus, there is a need for a 5V tolerant corner clamp that does not falsely trigger when a 5V signal is driven onto a signal pad.
SUMMARY OF THE INVENTION
The present invention provides a 5V tolerant ESD corner clamp that does not falsely trigger when a 5V signal is driven onto a signal pad. A corner clamp in accordance with the present invention includes a clamp circuit that is connected to an electrostatic discharge (ESD) plus ring and an ESD minus ring.
The clamp circuit has a timing circuit that has a resistive element that is connected to the ESD plus ring and a first node. The clamp circuit also has a pre-driver circuit that is connected to the timing circuit. The pre-driver circuit includes a first transistor that is connected to the ESD plus ring. The first transistor turns on when a difference between a voltage on the ESD plus ring and a voltage on the first node exceeds a predetermined amount. The clamp circuit further has a switching circuit that is connected to the pre-driver circuit, the ESD plus ring, and the ESD minus ring.
The corner clamp of the present invention also includes a keep off circuit that is connected to the clamp circuit, the ESD plus ring, and the ESD minus ring. The keep off circuit has a control circuit that is connected to the first node. The control circuit has an output. In addition, the keep off circuit inclu

Affiliated with

Also associated with

Rating

5V tolerant corner clamp with keep off circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with 5V tolerant corner clamp with keep off circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and 5V tolerant corner clamp with keep off circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3077020