50% duty-cycle clock generator

Details 50% duty-cycle clock generator 50% duty-cycle clock generator

2006-01-24

2006-01-24

Milord, Marceau (Department: 2682)

Pulse or digital communications

Testing

Phase error or phase jitter

C375S130000, C375S219000, C375S238000, C375S222000, C375S344000, C375S361000, C455S073000, C455S074000, C370S350000, C370S442000, C370S509000, C370S347000

Reexamination Certificate

active

06990143

ABSTRACT:
A method and apparatus for generating a fifty percent duty cycle clock from a reference clock. The method and apparatus includes an edge generator, a controllable delay module, a duty cycle control loop module and a reset circuit. The edge generator is coupled to generate a clean edge of the reference clock. The controllable delay module is coupled to produce a delayed edge from the clean edge based on a duty cycle control signal. The duty cycle control loop module is coupled to generate the duty cycle control signal based on the delayed edge and the reference clock signals. The reset circuit is coupled to reset the edge generator to produce a second edge. The second edge is delayed by the controllable delay module to produce a second delayed edge such that the delayed edge and the second delayed edge constitute one period of the fifty percent duty cycle clock.

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ISSCC94/Session 18 High-Performance Logic and Circuit Techniques.Paper FA 18.5.

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