5-to-2 binary adder

Details 5-to-2 binary adder 5-to-2 binary adder

2000-06-01

2003-06-10

Malzahn, David H. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S709000

Reexamination Certificate

active

06578063

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an apparatus for data processing in general, and in particular to a binary adder. Still more particularly, the present invention relates to a five-input/two-output binary adder.
2. Description of the Prior Art
The two most commonly encountered binary adders in digital arithmetic circuit arrangements are carry-propagate adders (CPAs) and carry-save adders (CSAs). CPAs are typically designed to have two data inputs and one output. CPAs operate according to well-known principles in which addend bits of the same order are added together, and a carry bit will be transferred to an adjacent higher order bit when required. A sum is directly derived from a bit-by-bit addition, with an appropriate carry to an adjacent higher order bit and a single bit carry out from the highest order bit position. The ripple carry of a CPA tends to result in slow non-parallel operations because high order bits computations are dependent on the results from low order bits.
CSAs, on the other hand, typically have three data inputs and two outputs. Carry bits in CSAs are accumulated separately from the sum bits of any given order (or position). The output of CSAs are two vectors, namely, a sum and a carry, which when added together yield the final result. One benefit of CSAs is that high-order bits have no dependency on any low-order bit because all bit positions are calculated independently, thereby avoiding the propagation latency associated with carry bits in CPAs. Because of their speed and simplicity, CSAs are pervasively found in digital logic designs.
The present disclosure describes a five-input/two-output CSA adder. Such five-input/two-output CSA adder can be advantageously used in, for example, a fused multiply-adder that combine a multiplication operation with an add operation.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a five-input/two-output binary adder includes five inputs and two outputs. Four levels of XOR logic gates are coupled between the five inputs and the two outputs for combining values received at the-five inputs and generating a sum value and a carry value at the outputs.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.


REFERENCES:
patent: 3535502 (1970-10-01), Clapper
patent: 5805491 (1998-09-01), Bechade
patent: 5818747 (1998-10-01), Wong
patent: 6308195 (2001-10-01), Hirase et al.
patent: 6345286 (2002-02-01), Dhong et al.
patent: 2002/0038327 (2002-03-01), Ferroussat
patent: 2002/0129077 (2002-09-01), Rhee
Hsiao et al “Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers” Electronics Letters vol. 34 No. 4 pp. 341-343 Feb. 19, 1998.*
Mori et al., “A 10-NS 54×54-B Parallel Structured Full Array Multiplier with 0.5um CMOS Technology,” IEEE Journal of Solid State Circuits, vol. 26, No. 4, 1991, pp. 600-606.
Law et al., “A Low-Power 16×16-B Parallel Multiplier Utilizing Pass-Transistor Logic”, IEEE Journal of Solid State Circuits, vol. 34, No. 10, Oct. 1999, pp. 1395-1399.
Izumikawa et al., “A 0.25um CMOS 0.9-V 100-MHz DSP Core”, IEEE Journal of Solid State Circuits, vol. 32, No. 1, Jan. 1997, pp. 52-61.
Yano et al., “A 3.8-ns CMOS 16×16-B Multiplier Using Complementary Pass-Transistor Logic”, IEEE Journal of Solid State Circuits, vol. 25, No. 2, Apr. 1990, pp. 388-395.
Song et al., “Circuit and Architecture Trade-Offs for High-Speed Multiplication,” IEEE Journal of Solid State Circuits, vol. 26, No. 9., Sep. 1991, pp. 1184-1198.

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