Coded data generation or conversion – Digital code to digital code converters – To or from multi-level codes
Reexamination Certificate
2000-07-25
2002-02-19
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from multi-level codes
C375S288000
Reexamination Certificate
active
06348882
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to signal and data transmission technology and, more particularly, to multiple level encoding and the conversion of encoded digital signals into binary equivalents.
BACKGROUND OF THE INVENTION
Signal transmission of data at high frequency rates, such as at exemplary rates of 4×10
9
bits/second, can generate problems. At such high frequency rates, line losses are higher. Secondly, electromagnetic interference (EMI) is generally higher. High line losses and high EMI tend to be undesirable consequences of high frequency data transmission rates. In contrast, jitter tends to be worse when clock power is relatively low. However, increased levels of clock power tend to correspond with relatively high frequency data transmission rates. Hence, attempts to achieve relatively low line loss and reduced EMI, in combination with reduced jitter, appear to present a conflict where traditional signal transmission techniques are employed.
Accordingly, a compromise is needed that enables the realization of relatively low line losses and reduced EMI while, at the same time, realizing reduced jitter. One technique involves the use of multiple level signaling schemes.
SUMMARY OF THE INVENTION
A system is provided for converting a multiple level encoded digital signal into a binary equivalent. A system of differential comparators are used to compare a differential input signal for purposes of extracting multiple level coding.
According to one aspect of the invention, a signal converter is provided for converting multiple level encoded digital signals into a binary equivalent. The signal converter includes a reference voltage generator, a plurality of differential comparators, error recovery circuitry, and signal conversion circuitry. The reference voltage generator is operative to generate a plurality of progressively larger differential reference voltages. The plurality of differential comparators are operative to compare a differential input voltage with the reference voltages and produce differential output voltages having first logical senses if the input voltage is greater than the reference voltages, and having second logical senses if the input voltage is less than the reference voltages, respectively. Furthermore, each comparator has an offset input voltage. The error recovery circuitry is configured to receive the differential output voltages from the differential comparators, and is operative to recover the clock via edge detection and generate a recovered clock signal. The signal conversion circuitry is coupled with the error recovery circuitry and the differential comparators, and is operative to convert the differential output voltages into a three-bit binary equivalent.
According to one aspect, a signal converter is provided for converting multiple level encoded digital signals into a binary equivalent signal. The signal converter includes a reference voltage generator, a plurality of four-input differential comparators, timing recovery circuitry, and signal conversion circuitry. The reference voltage generator is operative to generate a plurality of progressively larger differential reference voltages. The plurality of differential comparators are each operative to compare magnitude of a differential input voltage with magnitude of a dedicated one of the progressively larger differential reference voltages and produce a differential output voltage having a first logical sense if the magnitude of the differential input voltage is greater than the magnitude of the differential reference voltage, and having a second logical sense if the magnitude of the differential input voltage is less than the magnitude of the differential reference voltage. Each comparator has an offset input voltage. The timing recovery circuitry is configured to receive the differential output voltages from each of the differential comparators and is operative to derive a clock via edge detection and generate a recovered clock signal. The signal conversion circuitry is coupled with the timing recovery circuitry and the differential comparators and is operative to convert the differential output voltages into a binary equivalent.
According to another aspect of the invention, a method is provided for converting an (N+1)-level encoded digital signal into a binary equivalent signal. The method includes: generating N progressively larger differential reference signals; comparing the (N+1)-level differential input signal with each of the N reference signals; for each compared N reference signal, producing a differential output signal having first logical senses if the input signal is greater than the reference signal and having second logical senses if the input signal is less than the reference signal; generating a clock by edge detecting the N differential output signals so as to recover a clock signal; and converting the N differential output signals into a binary equivalent signal.
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patent: 5946355 (1999-08-01), Baker
patent: 6226330 (2001-05-01), Mansur
Ciccone John Charles
Liepold Carl
Sessions D.C.
Philips Electronics North America Corporation
Wells, St. John, Roberts Gregory & Matkin P.S.
Williams Howard L.
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