40 Gbit/s SONET framer with multiple clock-crossing capability

Details 40 Gbit/s SONET framer with multiple clock-crossing capability 40 Gbit/s SONET framer with multiple clock-crossing capability

2000-12-01

2004-04-27

Negash, Kinfe-Michael (Department: 2633)

Optical communications

Transmitter and receiver system

Including synchronization

C398S050000, C398S056000, C398S155000, C370S509000

Reexamination Certificate

active

06728492

ABSTRACT:

FIELD OF THE INVENTION
The present invention is generally related to optical communications systems, and more particularly to optical cross-connect systems receiving multiple streams of asynchronous data that are not synchronized with respect to each other or with respect to a system clock of the cross-connect.
BACKGROUND OF THE INVENTION
Optical cross-connect switches are utilized in optical communication systems and networks to redistribute a plurality of high data rate optical signals. For instance, in an optical OC-192 system a cross-connect switching matrix may be adapted to receive 64 STS-12 bitstreams, which requires the cross-connect to recover 16 separate clocks one for aggregates of 4 of these asynchronous data streams. The framer block provides the synchronization that receives data after the input stage of the system, and aligns the input data streams relative to the synchronization signal (SYNC), so that these multiple streams of data are ready for switching.
The problem lies in that the phase relationships between each of the 16 recovered clocks, typically recovered using a phase lock loop (PLL) circuit, and also with respect to a separate system clock, are totally random and thus unpredictable. Thus, one requirement of an optical cross-connect is to perform frame alignment of all 64 STS-12's and also retime the received STS-12 data streams with the system clock running at the same frequency, but at a different phase. That is, in an optical cross-connect system, there is required, on top of the switching block, some synchronization controllers that make sure this switching is done correctly at the proper time.
In larger system architectures, such as a high-speed, high density, 40 Gbit/s cross-connect, an ASIC is typically used. Conventionally, this ASIC has a high gate area consumption and power dissipation, especially in the case of many input frames (i.e. 64 STDS-12's).
One known solution is based upon sub-dividing the functional blocks of the cross-connect into three separate sub-blocks. Block
1
performs 16 byte alignments of 4 STS-12's each within each recovered clock domain. Block
2
moves the aligned bytes from the receiver clock domains into the unique system clock domain. Block
3
processes the synchronous bytes and sets them all on the same frame alignment. The order of Block
1
and Block
2
is interchangeable. However, in existing solutions, Block
2
requires at least three levels of data retiming, and Block
3
requires a number of retime stages that depends on a maximum input skew of the data, in this case being 3 retime stages. The problem with this approach is the high area of silicon consumption in an application specific integrated circuit (ASIC) and its associated power dissipation, which is significant when many input frames are provided, such as 64 STS-12's in a 40 Gbit cross-connect ASIC.
There is desired an approved solution having significant silicon area and operating power savings. The design should be generalized and usable for many input frames as desired. The design should be usable within a SONET/SDH environment.
SUMMARY OF THE INVENTION
The present invention achieves technical advantages as an optical cross-connect circuit and methodology whereby a framer block is configured such that the retiming stages necessary in both Block
2
and in Block
3
are shared, thereby reducing the area and power consumption of the whole Block. A uniquely located frame synchronization identifier (SYNC) is manipulated in Block
2
for the purpose of driving the clock-crossing control logic so that the data moves safely from the first time domain (receiver) to the second clock domain (transmitter), and at the same time get aligned. The framer block provides the synchronization that receives data after the input stage of the system, and aligns the input data streams relative to the synchronization signal (SYNC), so that these multiple streams of data are ready for switching. The framer has an input stage that parallelizes data to slow it down to ⅛ of the input data rate, such as using a 1-to-8 serial in parallel out (SIPO) based on the recovery clocks. This data comes from multiple sources, and the sources are not necessarily, and usually not, synchronized to each other, and thus, don't carry a clock with them due to the high speed characterization of this block.


REFERENCES:
patent: 6597214 (2003-07-01), Singh et al.
patent: 6647026 (2003-11-01), Tanaka
patent: 2001/0038476 (2001-11-01), Wolf
patent: 2 339 463 (2002-09-01), None

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