4-2 Compressor

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C708S708000

Reexamination Certificate

active

07035893

ABSTRACT:
A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a first plurality of transistor paths connecting each of the first plurality of inputs to the summation output. The compressor also includes a successive compressor, in which the successive compressor includes a second plurality of inputs and a plurality of successive transistor paths connecting at least one of the first plurality of inputs to the first carry bit output and connecting the first carry bit output to at least one of the second plurality of inputs. In one embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than seven and a successive compressor critical transistor stage path level within the successive compressor is less than eight. In another embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than eight and a successive compressor critical transistor stage path level within the successive compressor is less than seven.

REFERENCES:
patent: 4556948 (1985-12-01), Mercy
patent: 5818747 (1998-10-01), Wong
patent: 6308195 (2001-10-01), Hirase et al.
patent: 6584485 (2003-06-01), Aoki et al.
patent: 6615229 (2003-09-01), Vijayrao et al.
Norio Ohkubo,. et al.;A 4.4 ns CMOS 54×54-b Multiplier Using Pass-Transistor Multiplexer, IEEE Journal of Solid-State Circuits, vol. 30, No. 3, Mar. 1995, pp. 251-257.
Debabrata Ghosh, et al.;TWTXBb: A Low Latency, High Throughput Multiplier Architecture Using a New 4 → 2 Compressor, 7thInt'l Conf. on VLSI Design, Jan. 1994, pp. 77-82.
Masanori Izumikawa, et al.;A 0.25-μm CMOS 0.9-V 100-MHz DSP Core, IEEE Journal of D-Siate Circuits, vol. 32, No. 1, Jan., 1997, pp. 52-61.
Shen-Fu Hsiao, et al.;Design of High-Speed Low-Power 3-2 Counter and 4-2 Compressor for Fast Multipliers, Electronics Letters, vol. 34, No. 4, Feb. 19, 1998, pp. 341-433.

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