Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2006-04-25
2006-04-25
Ngo, Chuong D (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S708000
Reexamination Certificate
active
07035893
ABSTRACT:
A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a first plurality of transistor paths connecting each of the first plurality of inputs to the summation output. The compressor also includes a successive compressor, in which the successive compressor includes a second plurality of inputs and a plurality of successive transistor paths connecting at least one of the first plurality of inputs to the first carry bit output and connecting the first carry bit output to at least one of the second plurality of inputs. In one embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than seven and a successive compressor critical transistor stage path level within the successive compressor is less than eight. In another embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than eight and a successive compressor critical transistor stage path level within the successive compressor is less than seven.
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Awaka Kaoru
Takahashi Hiroshi
Toyonoh Yutaka
Brady III W. James
Marshall, Jr. Robert D.
Ngo Chuong D
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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