3D stack of IC chips having leads reached by vias through passiv

Details 3D stack of IC chips having leads reached by vias through passiv 3D stack of IC chips having leads reached by vias through passiv

1996-03-26

1997-11-18

Graybill, David

Fishing, trapping, and vermin destroying

437208, 437915, H01L 21283, H01L 2156, H01L 2160, H01L 2170

Patent

active

056887213

ABSTRACT:
A process in which a plurality of IC chips are stacked in a unitary structure having a novel method of exposing leads on the access plane of the stack. After a layer of dielectric material has been formed on the access plane, trenches (preferably trenches) are formed, e.g., by wet lithographic processing, which expose the access plane leads. Thereafter terminals are formed on the access plane in contact with the leads. At the wafer level, layers of dielectric material are deposited which are sufficiently thick to permit the subsequent forming of trenches in the access plane dielectric without uncovering any of the silicon of the IC chips.

REFERENCES:
patent: 3029495 (1962-04-01), Doctor
patent: 3370203 (1968-02-01), Kravitz et al.
patent: 4525921 (1985-07-01), Carson et al.
patent: 4617160 (1986-10-01), Belanger et al.
patent: 4672737 (1987-06-01), Carson et al.
patent: 5104820 (1992-04-01), Go et al.
patent: 5107586 (1992-04-01), Eichelberger et al.
patent: 5149419 (1992-09-01), Sexton et al.
patent: 5279991 (1994-01-01), Minahan et al.

Affiliated with

Also associated with

Rating

3D stack of IC chips having leads reached by vias through passiv does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with 3D stack of IC chips having leads reached by vias through passiv, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and 3D stack of IC chips having leads reached by vias through passiv will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1565290