3D interconnection process for electronic component packages and

Details 3D interconnection process for electronic component packages and 3D interconnection process for electronic component packages and

1993-09-21

1996-06-11

Thompson, Gregory D.

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

165 803, 165185, 174 163, 257713, 257686, 257723, 257796, 361721, 361733, 361735, 361744, 361809, 361810, 361820, 361829, H05K 720

Patent

active

055262309

ABSTRACT:
A device and method for interconnection packages in a stack. Each package encapsulates, for example a semiconductor chip containing an integrated circuit, which for example may be a memory. The packages (2) which have connecting pins (21) are mounted on support grid (4) which preferably act as a heat shunt, and are stacked and linked to each other with a resin coating (5). A stack (3) is cut out so that the pins on the packages and one edge of the grids are flush with faces (31, 32) of the stack (3). Connections between the packages themselves, and between the packages and stack connecting pads, are made on the faces of the stack. The connecting pads are where necessary fitted with connecting pins.

REFERENCES:
patent: 3029495 (1962-04-01), Doctor
patent: 3370203 (1968-02-01), Kravitz et al.
patent: 4862249 (1989-08-01), Carlson
patent: 4868712 (1989-09-01), Woodman
patent: 5007842 (1991-04-01), Deak et al.
List of Applicants U.S. application and patents 1 page.

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