3-input Exclusive-OR gate circuit

Details 3-input Exclusive-OR gate circuit 3-input Exclusive-OR gate circuit

1987-06-22

1988-06-07

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307585, 371 49, H03K 1921

Patent

active

047498870

ABSTRACT:
The present invention is an Exclusive-OR circuit which uses a minimum number of components and which is particularly adapted for use as a building block for a parity checking circuit. The circuit only uses CMOS gates to reduce the number of included transistors.

REFERENCES:
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patent: 4367420 (1983-01-01), Foss et al.
patent: 4430737 (1984-02-01), Beranger et al.
patent: 4451922 (1984-05-01), Dearden et al.
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patent: 4541067 (1985-09-01), Whitaker
patent: 4558236 (1985-12-01), Burrows
patent: 4575648 (1986-03-01), Lee
patent: 4617477 (1986-10-01), DePaolis, Jr.
patent: 4646306 (1987-02-01), Davis et al.
patent: 4710649 (1987-12-01), Lewis
Puri et al, "Three-Input Exclusive OR", IBM T.D.B., vol. 24, No. 7A, Dec. 1981, p. 3114.
"CMOS Transfer Gate Exclusive OR Circuit", IBM T.D.B., vol. 28, No. 10, Mar. 1986, pp. 4303-4304.
Griffin et al, "Three-Way Exclusive-OR Circuit", IBM T.D.B., vol. 25, No. 11B, Apr. 1983, pp. 6062-6063.

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