3-input arithmetic logic unit

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C708S518000

Reexamination Certificate

active

07149768

ABSTRACT:
A 3-input adder/subtractor unit, having a first input for receiving a first operand A, a second input for receiving a second operand B, and a third input for receiving a third operand C. An add/subtract unit includes a control input for receiving a user-specified opcode, a first 3-to-2 compressor for receiving a respective least significant bit of said operands or its complement, and a Half Adder coupled to the first 3-to-2 compressor and responsive to an output thereof and to said opcode for outputting a least significant bit of a sum equal to A+B+C or A+B−C or A−B+C or A−B−C. A plurality of 3-to-2 compressors each in respect of remaining bits of the operands receive a respective bit of the operands or its complement, and a 2-input adder coupled to the 3-to-2 compressors receive respective carry and save outputs thereof and computing respective bits of the sum apart from the least significant bit.

REFERENCES:
patent: 4707800 (1987-11-01), Montrone et al.
patent: 5327369 (1994-07-01), Ashkenazi
patent: 5883824 (1999-03-01), Lee et al.
patent: 6003125 (1999-12-01), Shippy
patent: 6260055 (2001-07-01), Sugeno et al.
patent: 6292818 (2001-09-01), Winters
patent: 6449629 (2002-09-01), Morgan
patent: 6748411 (2004-06-01), Hakami

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