Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...
Reexamination Certificate
1998-05-04
2001-07-03
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including high voltage or high power devices isolated from...
C257S265000, C257S272000, C257S337000, C257S500000, C257S502000
Reexamination Certificate
active
06255710
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to smart power ICs and more particularly to the fabrication of power semiconductor devices and control circuitry on the same substrate.
BACKGROUND OF THE INVENTION
Semiconductor power devices and, in particular, GaAs vertical power devices require conductive substrates so that one of the current carrying terminals (e.g. the drain) can be positioned on the reverse side. Control circuitry including field effect transistors (FETs), are generally included for controlling the power devices. However, GaAs control devices are usually fabricated using a plurality of thin epitaxial layers grown on a semi-insulating substrate. Thus, integration of the power devices and the control devices on a common substrate is not normally convenient.
In the past, integration of power and control devices has been accomplished by implanting a P-type well in an N-type substrate. Power devices are then fabricated in the conducting substrate and N-channel FETs, or control devices are fabricated in the P-type well. These circuits have poor isolation and there is a tendency to create parasitic junctions which substantially degrade the operation or require additional compensating structure. Also, the implanted wells use large amounts of substrate, so that the level of integration is very poor.
Another solution for combining power and control circuits on a common substrate is to form a large buried gate structure for the vertical power devices. The buried gate structure generally includes a p-type buried layer formed by implant, epitaxial growth etc. A portion of the buried gate structure is then used to isolate the control circuitry, which is fabricated above the portion of the buried gate structure, by including a vertical implant extending from the surface to the portion of the buried gate structure between the vertical power devices and the control devices. In this structure the buried gate and the vertical implant form a P-type isolation barrier beneath the control devices and between the control and power devices. This type of combination also has poor isolation and there is a tendency to create parasitic junctions which substantially degrade the operation or require additional compensating structure. Further, the implanted wells again use large amounts of substrate, so that the level of integration is very poor.
Thus, it would be highly desirable to provide high level integration of vertical power devices and control circuitry on a common substrate.
It is a purpose of the present invention to provide a new and improved integrated smart power IC.
It is another purpose of the present invention to provide a new and improved integrated smart power IC with improved isolation.
It is still another purpose of the present invention to provide a new and improved integrated smart power IC with a higher level of integration than prior art circuits and with reduced die size.
It is a further purpose of the present invention to provide a new and improved integrated smart power IC in which the isolation is relatively easy and inexpensive to fabricate.
SUMMARY OF THE INVENTION
The above problems and others are at least partially solved and the above purposes and others are realized in an integrated smart power circuit including a power semiconductor device fabricated on a conducting substrate with a first current carrying terminal positioned adjacent the upper surface of the substrate, a control terminal positioned between the upper and lower surfaces, and a second current carrying terminal positioned adjacent the lower surface of the substrate. A high resistance layer is formed on a portion of the upper surface of the substrate, either directly overlying or adjacent to the power device, and doped semiconductor material is positioned on the high resistance layer. Control circuitry is formed in the doped semiconductor material.
In a specific embodiment, the high resistance layer can be conveniently formed by growing a layer of AlAs and growing doped layers on the AlAs. The AlAs can be easily oxidized thereafter. In another embodiment, a layer of low temperature GaAs is formed on the upper surface of the substrate followed by an AlGaAs buffer layer and a GaAs channel layer.
REFERENCES:
patent: 5373522 (1994-12-01), Holonyak, Jr. et al.
patent: 5400354 (1995-03-01), Ludowise et al.
patent: 5473181 (1995-12-01), Schwalke et al.
E. I. Chen et al., “AlXGa1-XAs-GaAs Metal-Oxide Semiconductor Field Effect Transistors Formed By Lateral Water Vapor Oxidation of AIAs”, Appl. Phys. Lett, vol. 66, No. 20, May 15, 1995, pp. 2688-2690.
El-Zein Nada
Weitzel Charles E.
Koch William E.
Loke Steven
Martinez Anthony M.
Motorola Inc.
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