Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Reexamination Certificate
2001-11-12
2004-02-10
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
C345S531000, C345S568000
Reexamination Certificate
active
06690377
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention pertains in general to 3-D graphics engines and more particularly, to a 3-D graphics engine that utilizes embedded DRAM for processing information internal to a graphics integrated circuit.
BACKGROUND OF THE INVENTION
Due to recent advances in computer performance in the area of processing speeds, graphic systems have been improved to provide more realistic graphical images to operate with such things as home video games and the such. In these graphic systems, the data is processed to “render” or draw graphic primitives to the display of a system. These graphic primitives constitute the basic components of a graphics picture, such as a triangle or any type of polygon. It is the combination of these graphic primitives that is utilized to perform this rendering operation.
During the rendering operation, a frame buffer is utilized to store all the information for a given frame, the frame being mapped substantially to the display of the user. This frame buffer will therefore include all of the information that is necessary to interface with the display and allow the display to be written in the desired manner. During the rendering operation, these frame buffers must be accessed a number of times in order to create the final values that are to be output to the display. In the rendering operation, there are multiple operations that must be undertaken. Each of these operations requires access to the frame buffer or memory to Write data thereto or Read data therefrom. As the graphic systems become more complex, and more complex algorithms are utilized, access to the memory becomes the “bottleneck” to the overall operation of the system. Typically, there will be provided some type of bus structure that will interface with the memory. As the resolution increases in the graphic systems, more and more memory is required for storing the various information required for the rendering process. This memory tends to be external to the rendering engine and there is typically only provided a single bus that provides access to the memory, which bus usually has a defined width and data rate. Further, when a substantial amount of processing is provided on a single integrated circuit, the bus width becomes more problematic due to the number of pins on the integrated circuit that must be dedicated to interface with the external memory. Even though some memory could be included on the integrated circuit, as the memory requirements increase, they tend to exceed the capabilities of the semiconductor processing technology required for this 3-D rendering engine.
SUMMARY OF THE INVENTION
The present invention disclosed and claimed herein, in one aspect thereof, comprises a graphics engine. The graphics engine includes a rendering engine for receiving graphics primitives and converting them to pixel information for transfer to a display, The rendering engine is operable to access memory locations with multiple memory access requests for a Read or a Write operation and operable in a first address space. A plurality of memory blocks are provided, each individually accessible and all configured in a virtual address space different than said first address space. A memory mapping device is provided for mapping each of the memory requests to the virtual address space. A pipeline engine is operable to pipeline the mapped memory access requests for both Read and Write operations in accordance with a predetermined pipelining scheme. The memory access requests are received in parallel and processed asynchronously, such that access to more than one of the memory blocks can occur at substantially the same time.
REFERENCES:
patent: 5623692 (1997-04-01), Priem et al.
patent: 6215497 (2001-04-01), Leung
patent: 6295068 (2001-09-01), Peddada et al.
patent: 6329997 (2001-12-01), Wu et al.
patent: 2001/0008400 (2001-07-01), Moriwaki et al.
Bitboys Oy
Howison & Arnott , L.L.P.
Tung Kee M.
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