3-D readout-electronics packaging for high-bandwidth...

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material

Reexamination Certificate

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Details

C257S072000, C257S083000, C257S258000, C257S292000

Reexamination Certificate

active

10901309

ABSTRACT:
Dense, massively parallel signal processing electronics are co-packaged behind associated sensor pixels. Microchips containing a linear or bilinear arrangement of photo-sensors, together with associated complex electronics, are integrated into a simple 3-D structure (a “mirror cube”). An array of photo-sensitive cells are disposed on a stacked CMOS chip's surface at a 45° angle from light reflecting mirror surfaces formed on a neighboring CMOS chip surface. Image processing electronics are held within the stacked CMOS chip layers. Electrical connections couple each of said stacked CMOS chip layers and a distribution grid, the connections for distributing power and signals to components associated with each stacked CSMO chip layer.

REFERENCES:
patent: 6355976 (2002-03-01), Faris
patent: 6821808 (2004-11-01), Nakamura et al.
patent: 2003/0123792 (2003-07-01), Matsumoto et al.

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