3-D graphics chip with embedded DRAM buffers

Details 3-D graphics chip with embedded DRAM buffers 3-D graphics chip with embedded DRAM buffers

2005-08-30

2005-08-30

Tung, Kee M. (Department: 2676)

Computer graphics processing and selective visual display system

Computer graphic processing system

Integrated circuit

C345S544000, C345S558000

Reexamination Certificate

active

06937242

ABSTRACT:
A 3-D graphics chip includes independent internal DRAM buffers each having a wide bandwidth access bus for connection to a 3-D texture rendering drawing engine. The 3-D drawing engine takes advantage of a flexible embedded memory interface to reduce the traditional 3-D pipeline delay by a factor of 3. In a specific embodiment, each of three drawing processes—texture, Z, pixel—retrieves and stores information in a separate embedded drawing buffer via separate wide bandwidth access busses. Access to an external memory is provided via a separate external access bus. In another specific embodiment, the 3-D drawing engine accesses the embedded drawing buffers via read and write FIFO's to maximize the drawing process throughput.

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Junko Yoshida, “Startup Turns Up Heat in 3-D Graphics Chips”, Aug. 17, 1998, Electronic Engineering Times, p. 26.

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