3-1 Arithmetic logic unit for simultaneous execution of an indep

Details 3-1 Arithmetic logic unit for simultaneous execution of an indep 3-1 Arithmetic logic unit for simultaneous execution of an indep

1994-01-24

1995-06-20

Kim, Ken S.

Boots, shoes, and leggings

364736, 364787, 364DIG1, 364DIG2, 395775, 395800, G06F 930

Patent

active

054267439

ABSTRACT:
A high speed three-to-one data dependency collapsing ALU can be used to support multiple issue of instructions. The computing apparatus supports multiple issue of instructions it is useful in CISC, superscalar, superscalar RISC, etc. type computer designs. The concept of the ALU is presented along with a detailed description of a design. The apparatus allows the execution of any combination of two independent or dependent arithmetic or logical instructions in a single machine cycle. The 3-1 collapsing ALU structure has a 3-2 carry save adder (CSA); and a 2-1 control arithmetic logic unit (CALU) coupled for an input from the carry save adder; and a first pre-adder logic block coupled with an output to the control arithmentic logic unit; and a control generator; and a second controlled logic block coupled to receive an input from said control generator and having its output coupled to said control arithmetic logic unit. Instructions have an add/logical combinatorial operation which combines all four of the combinations: add-add, add-logical, logical-add, and logical-logical functions; and wherein two or more disassociated ALU operations are specified by a single interlock collapsing ALU which responds to the parallel issuance of a plurality of separate instructions, including RISC type instructions, each of which specifies ALU operations, and the computing apparatus executes the instructions in parallel in a single machine cycle.

REFERENCES:
patent: 4110832 (1978-08-01), Leininger et al.
patent: 4819155 (1989-04-01), Wulf et al.
patent: 4852040 (1989-07-01), Oota
patent: 4958312 (1990-09-01), Ang et al.

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