Image analysis – Applications – 3-d or stereo imaging analysis
Reexamination Certificate
1998-09-14
2003-06-24
Johnson, Timothy M. (Department: 2625)
Image analysis
Applications
3-d or stereo imaging analysis
C382S103000, C382S285000, C345S422000, C348S024000, C348S169000, C396S324000, C396S377000
Reexamination Certificate
active
06584219
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a 2D/3D image conversion system for converting two-dimensional images into three-dimensional images.
2. Related Art
There has been known a method of converting two-dimensional (2D) images into three-dimensional (3D) images including the steps of: generating, from a 2D image signal, a main image signal and a sub-image signal time-delayed relative to the main image signal by utilizing a plurality of field memories; and outputting either one of the main and sub-image signals as a left-eye image signal and the other as a right-eye image signal.
A time delay of the sub-image signal relative to the main image signal (hereinafter referred to as “delay value”) is determined based on a velocity of horizontal motion of the main image. That is, the greater the velocity of horizontal motion of the main image, the smaller the delay value. Further, which of the main image and the sub-image is represented by the left-eye image signal with the other represented by the right-eye image signal is determined based on a direction (leftward or rightward) of the horizontal motion of the main image.
Since such a method is adapted to convert only 2D moving images into 3D images, this method is referred to as “2D/3D moving image conversion method”.
The present applicants have already developed a method of converting 2D still images into 3D images (hereinafter referred to as “2D/3D still image conversion method”), having filed an application for patent (Japanese Patent Application No.9(1997)-159949). However, having not yet been laid open, this application does not constitute the prior art.
This 2D/3D still image conversion method includes the steps of: extracting from a 2D input image signal a perspective image characteristic value of each of a plurality of parallax calculation regions defined in a one-field screen, the extraction performed on a field-by-field basis; generating parallax information per given unit area in the one-field screen based on the image characteristic value per parallax calculation region thus extracted; and generating a first image signal and a second image signal from a signal residing in each of the given unit areas of the 2D input image, the first and second image signals having a horizontal phase difference therebetween based on the parallax information corresponding to the given unit area.
Now referring to
FIGS. 1
to
3
, description will be made on the 2D/3D still image conversion method (Japanese Patent Application No.9(1997)-159949) developed by the applicants. It is to be noted that this 2D/3D still image conversion method has not yet been known to the art and hence, does not constitute the prior art.
FIG. 1
is a block diagram showing a whole construction of a 2D/3D image conversion system for converting 2D images into 3D images.
A luminance signal Y and color difference signals R-Y and B-Y constituting a 2D image signal are respectively converted into digital signals Y, R-Y and B-Y by means of an AD conversion circuit
1
(ADC).
The Y signal is supplied to a high-frequency component integrating circuit
8
and a luminance contrast calculating circuit
9
as well as to a first left-eye-image optional pixel delay FIFO
11
and a first right-eye-image optional pixel delay
21
. The R-Y signal is supplied to an R-Y component integrating circuit
31
as well as to a second left-eye-image optional pixel delay FIFO
12
and a second right-eye-image optional pixel delay FIFO
22
. The B-Y signal is supplied to a B-Y component integrating circuit
32
as well as to a third left-eye-image optional pixel delay FIFO
13
and a third right-eye-image optional pixel delay FIFO
23
.
As shown in
FIG. 2
, the high-frequency component integrating circuit
8
performs calculation on a field-by-field basis for giving an integrated value of high-frequency component of each of the plural parallax calculation regions E
1
to E
12
previously defined in the one-field screen. The luminance contrast calculating circuit
9
calculates a luminance contrast of each of the parallax calculation regions E
1
to E
12
on a field-by-field basis. The R-Y component integrating circuit
31
calculates an integrated value of R-Y component of each of the parallax calculation regions E
1
to E
12
on a field-by-field basis. The B-Y component integrating circuit
32
calculates an integrated value of B-Y component of each of the parallax calculation regions E
1
to E
12
on a field-by-field basis.
The high-frequency component integration values, luminance contrasts, R-Y component integrated values and B-Y component integrated values of the respective parallax calculation regions E
1
to E
12
are used as perspective image characteristic values of the respective parallax calculation regions E
1
to E
12
.
In an example shown in
FIG. 13
, the one-field screen includes a total of 60 parallax calculation regions in 6 rows and 10 columns. However, it is assumed for convenience in explanation that a total of 12 parallax calculation regions E
1
to E
12
in 3 rows and 4 columns are defined in a one-field screen, as shown in FIG.
2
.
A CPU
3
generates parallax information on the respective parallax calculation regions E
1
to E
12
based on information supplied from the high-frequency component integrating circuit
8
, luminance contrast calculating circuit
9
, R-Y component integrating circuit
31
and B-Y component integrating circuit
32
. In this example, the parallax information is generated such that the more to the front is located an object like a subject in a scene of the example, the smaller is the parallax value while the more to the back is located an object like a background of the scene of the example, the greater is the parallax value. A method of generating the parallax information will hereinafter be described in detail.
The parallax information per parallax calculation region E
1
to E
12
thus given by the CPU
3
is sent to a parallax control circuit
4
. The parallax control circuit
4
, in turn, generates parallax information per pixel position in each field based on the parallax information on the respective parallax calculation regions E
1
to E
12
. Based on the parallax information per pixel position, the parallax control circuit
4
controls readout addresses of FIFOs
11
to
13
and
21
to
23
so as to read out an image signal(Y, R-Y and B-Y signals) from the left-eye-image optional pixel delays FIFOs
11
to
13
and from the right-eye-image optional pixel delays FIFOs
21
to
23
, respectively, with the addresses of FIFOs
11
to
13
and of FIFOs
21
to
23
shifted from each other. Hence, left-eye image signals read out from the left-eye-image optional pixel delays FIFOs
11
to
13
have different horizontal phases from right-eye image signals read out from the right-eye-image optional pixel delays FIFOs
21
to
23
.
The left-eye image signals (YL signal, (R-Y)L signal and (B-Y)L signal) read out from the left-eye-image optional pixel delays FIFOs
11
to
13
are converted into analog signals through a DA conversion circuit (DAC)
5
before supplied to an unillustrated three-dimensional display unit. The right-eye image signals (YR signal, (R-Y)R signal and (B-Y)R signal) read out from the right-eye-image optional pixel delays FIFOs
21
to
23
are converted into analog signals through a DA conversion circuit (DAC)
6
before supplied to the unillustrated three-dimensional display unit.
Since the left-eye image signal has a different horizontal phase from that of the right-eye image signal, a parallax is produced between the left eye image and the right eye image. Hence, by viewing the left eye image with the left eye alone and the right eye image with the right eye alone, a three-dimensional image is established wherein the subject is located to the front against the background.
FIG. 3
diagrammatically illustrates a configuration of the R-Y component integrating circuit
31
.
FIG. 2
shows horizontal positions (HAD) and vertical positions (VAD) wherein a number of hori
Mori Yukio
Murata Haruhiko
Okada Seiji
Yamashita Syuugo
Arent Fox Kintner Plotkin & Kahn
Chawan Sheela
Johnson Timothy M.
Sanyo Electric Co,. Ltd.
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