276-pin buffered memory module with enhanced fault tolerance

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S051000, C365S052000, C361S728000

Reexamination Certificate

active

07403409

ABSTRACT:
A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.

REFERENCES:
patent: 3825904 (1974-07-01), Burk et al.
patent: 4475194 (1984-10-01), LaVallee et al.
patent: 4486739 (1984-12-01), Franaszek et al.
patent: 4723120 (1988-02-01), Petty, Jr.
patent: 4740916 (1988-04-01), Martin
patent: 4833605 (1989-05-01), Terada et al.
patent: 4839534 (1989-06-01), Clasen
patent: 4943984 (1990-07-01), Pechanek et al.
patent: 4985828 (1991-01-01), Shimizu et al.
patent: 5053947 (1991-10-01), Heibel et al.
patent: 5214747 (1993-05-01), Cok
patent: 5287531 (1994-02-01), Rogers, Jr. et al.
patent: 5387911 (1995-02-01), Gleichert et al.
patent: 5454091 (1995-09-01), Sites et al.
patent: 5475690 (1995-12-01), Burns et al.
patent: 5513135 (1996-04-01), Dell et al.
patent: 5592632 (1997-01-01), Leung et al.
patent: 5611055 (1997-03-01), Krishan et al.
patent: 5613077 (1997-03-01), Leung et al.
patent: 5629685 (1997-05-01), Allen et al.
patent: 5661677 (1997-08-01), Rondeau, II et al.
patent: 5666480 (1997-09-01), Leung et al.
patent: 5822749 (1998-10-01), Agarwal
patent: 5872996 (1999-02-01), Barth et al.
patent: 5926838 (1999-07-01), Jeddeloh
patent: 5928343 (1999-07-01), Farmwald et al.
patent: 5995405 (1999-11-01), Trick
patent: 6049476 (2000-04-01), Laudon et al.
patent: 6076158 (2000-06-01), Sites et al.
patent: 6096091 (2000-08-01), Hartmann
patent: 6128746 (2000-10-01), Clark et al.
patent: 6170047 (2001-01-01), Dye
patent: 6170059 (2001-01-01), Pruett et al.
patent: 6292903 (2001-09-01), Coteus et al.
patent: 6317352 (2001-11-01), Halbert et al.
patent: 6321343 (2001-11-01), Toda
patent: 6338113 (2002-01-01), Kubo et al.
patent: 6370631 (2002-04-01), Dye
patent: 6378018 (2002-04-01), Tsern et al.
patent: 6393528 (2002-05-01), Arimilli et al.
patent: 6473836 (2002-10-01), Ikeda
patent: 6483755 (2002-11-01), Leung et al.
patent: 6493250 (2002-12-01), Halbert et al.
patent: 6496540 (2002-12-01), Widmer
patent: 6496910 (2002-12-01), Baentsch et al.
patent: 6502161 (2002-12-01), Perego et al.
patent: 6507888 (2003-01-01), Wu et al.
patent: 6510100 (2003-01-01), Grundon et al.
patent: 6513091 (2003-01-01), Blackmon et al.
patent: 6532525 (2003-03-01), Aleksic et al.
patent: 6549971 (2003-04-01), Cecchi et al.
patent: 6553450 (2003-04-01), Dodd et al.
patent: 6557069 (2003-04-01), Drehmel et al.
patent: 6564329 (2003-05-01), Cheung et al.
patent: 6601121 (2003-07-01), Singh et al.
patent: 6611905 (2003-08-01), Grundon et al.
patent: 6622217 (2003-09-01), Gharachorloo et al.
patent: 6625687 (2003-09-01), Halbert et al.
patent: 6625702 (2003-09-01), Rentscler et al.
patent: 6631439 (2003-10-01), Saulsbury et al.
patent: 6678811 (2004-01-01), Rentschler et al.
patent: 6697919 (2004-02-01), Gharachorloo et al.
patent: 6704842 (2004-03-01), Janakiraman et al.
patent: 6721944 (2004-04-01), Chaudhry et al.
patent: 6738836 (2004-05-01), Kessler et al.
patent: 6766389 (2004-07-01), Hayter et al.
patent: 6775747 (2004-08-01), Venkatraman
patent: 6791555 (2004-09-01), Radke et al.
patent: 6839393 (2005-01-01), Sidiropoulos
patent: 6877076 (2005-04-01), Cho et al.
patent: 6877078 (2005-04-01), Fujiwara et al.
patent: 6889284 (2005-05-01), Nizar et al.
patent: 6970968 (2005-11-01), Holman
patent: 6977536 (2005-12-01), Chin-Chieh et al.
patent: 7224595 (2007-05-01), Dreps et al.
patent: 7234099 (2007-06-01), Gower et al.
patent: 2001/0000822 (2001-05-01), Dell et al.
patent: 2001/0003839 (2001-06-01), Kondo
patent: 2002/0019926 (2002-02-01), Huppenthal et al.
patent: 2002/0038405 (2002-03-01), Leddige et al.
patent: 2002/0083255 (2002-06-01), Greeff et al.
patent: 2002/0103988 (2002-08-01), Dornier
patent: 2002/0112119 (2002-08-01), Halbert et al.
patent: 2002/0112194 (2002-08-01), Uzelac
patent: 2002/0124195 (2002-09-01), Nizar
patent: 2002/0147898 (2002-10-01), Rentschler et al.
patent: 2002/0174274 (2002-11-01), Wu et al.
patent: 2003/0033364 (2003-02-01), Garnett et al.
patent: 2003/0090879 (2003-05-01), Doblar et al.
patent: 2003/0223303 (2003-12-01), Lamb et al.
patent: 2003/0236959 (2003-12-01), Johnson et al.
patent: 2004/0006674 (2004-01-01), Hargis et al.
patent: 2004/0117588 (2004-06-01), Arimilli et al.
patent: 2004/0230718 (2004-11-01), Polzin et al.
patent: 2004/0246767 (2004-12-01), Vogt
patent: 2004/0260909 (2004-12-01), Lee et al.
patent: 2004/0260957 (2004-12-01), Jeddeloh et al.
patent: 2005/0050237 (2005-03-01), Jeddeloh et al.
patent: 2005/0050255 (2005-03-01), Jeddeloh
patent: 2005/0066136 (2005-03-01), Schnepper
patent: 2005/0080581 (2005-04-01), Zimmerman et al.
patent: 2005/0097249 (2005-05-01), Oberlin et al.
patent: 2005/0120157 (2005-06-01), Chen et al.
patent: 2005/0125702 (2005-06-01), Huang et al.
patent: 2005/0125703 (2005-06-01), Lefurgy et al.
patent: 2005/0144399 (2005-06-01), Hosomi
patent: 2005/0177690 (2005-08-01), LaBerge
patent: 2005/0229132 (2005-10-01), Butt et al.
patent: 2005/0259496 (2005-11-01), Hsu et al.
patent: 2008/0094808 (2008-04-01), Kanapathippillai et al.
Brown, et al “Compiler-Based I/O Prefetching for Out-of-Core Applications”, ACM Transactions on Computer Systems, vol. 19, No. 2, May 2001, pp. 111-170.
Ghoneima et al.; “Optimum Positioning of Interleaved Repeaters in Bidirectional Buses;” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, No. 3, Mar. 2005, pp. 461-469.
JEDEC Solid State Technology Association, “JEDEC Standard: DDR2 SDRAM Specification”, Jan. 2004, JEDEC, Revision JESD79-2A, p. 10.
Jungjoon Kim et al.; “Performance and Architecture Features of Segmented Multiple Bus System;” IEEE Computer Society; 1999 International Conference on Parallel Processing (ICPP '99).
Natarajan, et al., “A Study of Performance Impact of Memory Controller Features in Multi-Processor Server Environment”, pp. 80-87.
Nilsen, “High-Level Dynamic Memory Management for Object-Oriented Real-Time Systems”, pp. 86-93.
Penrod, Lee, “Understanding System Memory and CPU Speeds: A laymans guide to the Front Side Bus (FSB)”, Dec. 28, 2005, Direction . Org, pp. 1-5, http://www.directron.com/directron/fsbguide.html. [online]; [retrieved on Feb. 23, 2006]; retrieved from the Internet.
Seceleanu et al.; “Segment Arbiter as Action System;” IEEE 2003 pp. 249-252.
Sivencrona et al.; “RedCAN™: Simulations of two Fault Recovery Algorithms for CAN;” Proceedings for the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC'04); 2005.
Wang, et al., “Guided Region Prefetching: A Cooperative Hardware/Software Approach”, pp. 388-398.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

276-pin buffered memory module with enhanced fault tolerance does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with 276-pin buffered memory module with enhanced fault tolerance, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and 276-pin buffered memory module with enhanced fault tolerance will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2816157

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.