Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2002-05-16
2003-10-07
Tran, M. (Department: 2818)
Static information storage and retrieval
Format or disposition of elements
C365S226000
Reexamination Certificate
active
06631084
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to integrated circuit memory design and, more particularly, to dynamic random access memory (DRAM) designs.
2. Description of the Background
1. Introduction
Random access memories (RAMs) are used in a large number of electronic devices from computers to toys. Perhaps the most demanding applications for such devices are computer applications in which high density memory devices are required to operate at high speeds and low power. To meet the needs of varying applications, two basic types of RAM have been developed. The dynamic random access memory (DRAM) is, in its simplest form, a capacitor in combination with a transistor which acts as a switch. The combination is connected across a digitline and a predetermined voltage with a wordline used to control the state of the transistor. The digitline is used to write information to the capacitor or read information from the capacitor when the signal on the wordline renders the transistor conductive.
In contrast, a static random access memory (SRAM) is comprised of a more complicated circuit which may include a latch. The SRAM architecture also uses digitlines for carrying information to and reading information from each individual memory cell and wordlines to carry control signals.
There are a number of design tradeoffs between DRAM and SRAM devices. Dynamic devices must be periodically refreshed or the data stored will be lost. SRAM devices tend to have faster access times than similarly sized DRAM devices. SRAM devices tend to be more expensive than DRAM devices because the simplicity of the DRAM architecture allows for a much higher density memory to be constructed. For those reasons, SRAM devices tend to be used as cache memory whereas DRAM devices tend to be used to provide the bulk of the memory requirements. As a result, there is tremendous pressure on producers of DRAM devices to produce higher density devices in a cost effective manner.
2. DRAM Architecture
A DRAM chip is a sophisticated device which may be thought of as being comprised of two portions: the array, which is comprised of a plurality of individual memory cells for storing data and the peripheral devices, which are all of the circuits needed to read information into and out of the array and support the other functions of the chip. The peripheral devices may be further divided into data path elements, address path elements, and all other circuits such as voltage regulators, voltage pumps, redundancy circuits, test logic, etc.
A. The Array
Turning first to the array, the topology of a modern DRAM array
1
is illustrated in FIG.
1
. The array
1
is comprised of a plurality of cells
2
with each cell constructed in a similar manner. Each cell is comprised of a rectangular active area, which in
FIG. 1
is a N+ active area. A dotted box
3
illustrates where one transistor/capacitor pair is fabricated while a dotted box
4
illustrates where a second transistor/capacitor pair is fabricated. A wordline WL
1
runs through dotted box
3
, and at least a portion of where that wordline overlays the N+ active area is where the gate of the transistor is formed. To the left of the wordline WL
1
in dotted box
3
, one terminal of the transistor is connected to a storage node
5
which forms the capacitor. The other terminal of the capacitor is connected to a cell plate. To the right of the wordline WL
1
, the other terminal of the transistor is connected to a digitline D
2
at a digitline contact
6
. The transistor/capacitor pair in dotted box
4
is a mirror image of the transistor/capacitor pair in dotted box
3
. The transistor within dotted box
4
is connected to its own wordline WL
2
while sharing the digitline contact
6
with the transistor in the dotted box
3
.
The wordlines WL
1
and WL
2
may be constructed of polysilicon while the digitline may be constructed of polysilicon or metal. The capacitors may be formed with an oxide-nitride-oxide-dielectric between two polysilicon layers. In some processes, the wordline polysilicon is silicided to reduce the resistance which permits longer wordline segments without impacting speed.
The digitline pitch, which is the width of the digitline plus the space between digitlines, dictates the active area pitch and the capacitor pitch. Process engineers adjust the active area width and the resulting field oxide width to maximize transistor drive and minimize transistor-to-transistor leakage. In a similar manner, the wordline pitch dictates the space available for the digitline contact, transistor length, active area length, field poly width, and capacitor length. Each of those features is closely balanced by process engineers to maximize capacitance and yield and to minimize leakage.
B. The Data Path Elements
The data path is divided into the data read path and the data write path. The first element of the data read path, and the last element of the data write path, is the sense amplifier. The sense amplifier is actually a collection of circuits that pitch up to the digitlines of a DRAM array. That is, the physical layout of each circuit within the sense amplifier is constrained by the digitline, pitch. For example, the sense amplifiers for a specific digitline pair are generally laid out within the space of four digitlines. One sense amplifier for every four digitlines is commonly referred to as quarter pitch or four pitch.
The circuits typically comprising the sense amplifier include isolation transistors, circuits for digitline equilibration and bias, one or more N-sense amplifiers, one or more P-sense amplifiers, and I/O transistors for connecting the digitlines to the I/O signal lines. Each of those circuits will be discussed.
Isolation transistors provide two functions. First, if the sense amplifiers are positioned between and connected to two arrays, they electrically isolate one of the two arrays. Second, the isolation transistors provide resistance between the sense amplifier and the highly capacitive digitlines, thereby stabilizing the sense amplifier and speeding up the sensing operation. The isolation transistors are responsive to a signal produced by an isolation driver. The isolation driver drives the isolation signal to the supply potential and then drives the signal to a pumped potential which is equal to the value of the charge on the digit lines plus the threshold voltage of the isolation transistors.
The purpose of the equilibration and bias circuits is to ensure that the digitlines are at the proper voltages to enable a read operation to be performed. The N-sense amplifiers and P-sense amplifiers work together to detect the signal voltage appearing on the digitlines in a read operation and to locally drive the digitlines in a write operation. Finally, the I/O transistors allow data to be transferred between digitlines and I/O signal lines.
After data is read from an mbit and latched by the sense amplifier, it propagates through the I/O transistors onto the I/O signal lines and into a DC sense amplifier. The I/O lines are equilibrated and biased to a voltage approaching the peripheral voltage Vcc. The DC sense amplifier is sometimes referred to as the data amplifier or read amplifier. The DC sense amplifier is a high speed, high gain, differential amplifier for amplifying very small read signals appearing on the I/O lines into full CMOS data signals input to an output data buffer. In most designs, the array sense amplifiers have very limited drive capability and are unable to drive the I/O lines quickly. Because the DC sense amplifier has a very high gain, it amplifies even the slightest separation in the I/O lines into full CMOS levels.
The read data path proceeds from the DC sense amplifier to the output buffers either directly or through data read multiplexers (muxes). Data read muxes are commonly used to accommodate multiple part configurations with a single design. For an x
16
part, each output buffer has access to only one data read line pair. For an x
8
part, the eight output buffers each have t
Bunker Layne G.
Keeth Brent
Micro)n Technology, Inc.
Thorp Reed & Armstrong LLP
Tran M.
LandOfFree
256 Meg dynamic random access memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with 256 Meg dynamic random access memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and 256 Meg dynamic random access memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3111226