Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2011-06-28
2011-06-28
Tran, Michael T (Department: 2827)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230060
Reexamination Certificate
active
07969810
ABSTRACT:
A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to datalines. A data path is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.
REFERENCES:
patent: 3922569 (1975-11-01), Nabetani et al.
patent: 4142114 (1979-02-01), Green
patent: 4293950 (1981-10-01), Shimizu et al.
patent: 4419594 (1983-12-01), Gemmell et al.
patent: 4612564 (1986-09-01), Moyer
patent: 4651252 (1987-03-01), Babinski
patent: 4680613 (1987-07-01), Daniels et al.
patent: 4688191 (1987-08-01), Conners
patent: 4716323 (1987-12-01), Wada et al.
patent: 4744061 (1988-05-01), Takemae et al.
patent: 4780716 (1988-10-01), Motohashi et al.
patent: 4821238 (1989-04-01), Tatematsu
patent: 4860260 (1989-08-01), Saito et al.
patent: 4879688 (1989-11-01), Turner et al.
patent: 4905191 (1990-02-01), Arai
patent: 4918663 (1990-04-01), Remington et al.
patent: 4949213 (1990-08-01), Sasagawa et al.
patent: 4967394 (1990-10-01), Minagawa et al.
patent: 4970725 (1990-11-01), McEnroe et al.
patent: 5072138 (1991-12-01), Slemmer et al.
patent: 5120988 (1992-06-01), Matsuki
patent: 5155704 (1992-10-01), Walther et al.
patent: 5159273 (1992-10-01), Wright et al.
patent: 5177745 (1993-01-01), Rozman
patent: 5184031 (1993-02-01), Hayakawa et al.
patent: 5212440 (1993-05-01), Waller
patent: 5231605 (1993-07-01), Lee
patent: 5252507 (1993-10-01), Hively et al.
patent: 5266821 (1993-11-01), Chern et al.
patent: 5268815 (1993-12-01), Cipolla et al.
patent: 5278462 (1994-01-01), Wilson
patent: 5293077 (1994-03-01), Seki et al.
patent: 5335202 (1994-08-01), Manning et al.
patent: 5336947 (1994-08-01), Lehning
patent: 5337284 (1994-08-01), Cordoba et al.
patent: 5359557 (1994-10-01), Aipperspach et al.
patent: 5373227 (1994-12-01), Keeth
patent: 5373277 (1994-12-01), Naito
patent: 5379263 (1995-01-01), Ogawa et al.
patent: 5384784 (1995-01-01), Mori et al.
patent: 5389739 (1995-02-01), Mills
patent: 5400342 (1995-03-01), Matsumura et al.
patent: 5448199 (1995-09-01), Park
patent: 5448742 (1995-09-01), Bhattacharya
patent: 5457696 (1995-10-01), Mori
patent: 5467468 (1995-11-01), Koshikawa
patent: 5473277 (1995-12-01), Furumochi
patent: 5481179 (1996-01-01), Keeth
patent: 5481671 (1996-01-01), Fujisaki
patent: 5497112 (1996-03-01), Hoang
patent: 5517454 (1996-05-01), Sato et al.
patent: 5519360 (1996-05-01), Keeth
patent: 5526253 (1996-06-01), Duley
patent: 5526364 (1996-06-01), Roohparvar
patent: 5528125 (1996-06-01), Marshall et al.
patent: 5539702 (1996-07-01), Ahn
patent: 5552739 (1996-09-01), Keeth et al.
patent: 5554953 (1996-09-01), Shibayama et al.
patent: 5555249 (1996-09-01), Hilley et al.
patent: 5557579 (1996-09-01), Raad et al.
patent: 5568428 (1996-10-01), Toda
patent: 5572147 (1996-11-01), Huang et al.
patent: 5574697 (1996-11-01), Manning
patent: 5602794 (1997-02-01), Javanifard et al.
patent: 5604710 (1997-02-01), Tomishima et al.
patent: 5608674 (1997-03-01), Yabe et al.
patent: 5610869 (1997-03-01), Yoo et al.
patent: 5614859 (1997-03-01), Ong
patent: 5619122 (1997-04-01), Kearney et al.
patent: 5627716 (1997-05-01), Lagree et al.
patent: 5651011 (1997-07-01), Keeth
patent: 5657284 (1997-08-01), Beffa
patent: 5659748 (1997-08-01), Kennedy
patent: 5661729 (1997-08-01), Miyazaki et al.
patent: 5677645 (1997-10-01), Merritt
patent: 5698972 (1997-12-01), Keeth
patent: 5705947 (1998-01-01), Jeong
patent: 5706234 (1998-01-01), Pilch, Jr. et al.
patent: 5710741 (1998-01-01), McLaury
patent: 5715247 (1998-02-01), Nara et al.
patent: 5723999 (1998-03-01), Merritt
patent: 5724289 (1998-03-01), Watanabe
patent: 5751652 (1998-05-01), Tomita
patent: 5757175 (1998-05-01), Morishita et al.
patent: 5761145 (1998-06-01), Zagar et al.
patent: 5767735 (1998-06-01), Javanifard et al.
patent: 5817544 (1998-10-01), Parthasarathi
patent: 5818102 (1998-10-01), Rostoker
patent: 5838076 (1998-11-01), Zarrabian et al.
patent: 5838150 (1998-11-01), Keeth
patent: 5838627 (1998-11-01), Tomishima et al.
patent: 5841725 (1998-11-01), Kang et al.
patent: 5867505 (1999-02-01), Beffa
patent: 5874327 (1999-02-01), Rostoker et al.
patent: 5877651 (1999-03-01), Furutani
patent: 5880622 (1999-03-01), Evertt et al.
patent: 5886932 (1999-03-01), Choi
patent: 5901087 (1999-05-01), Pascucci
patent: 5901105 (1999-05-01), Ong et al.
patent: 5903173 (1999-05-01), Gottshall et al.
patent: 5903575 (1999-05-01), Kikuda
patent: 5905387 (1999-05-01), Chinosi et al.
patent: 5909141 (1999-06-01), Tomishima
patent: 5917348 (1999-06-01), Chow
patent: 5929694 (1999-07-01), Yanagawa et al.
patent: 5954804 (1999-09-01), Farmwald et al.
patent: 5960455 (1999-09-01), Bauman
patent: 5983375 (1999-11-01), Kim et al.
patent: 5999021 (1999-12-01), Jang
patent: 5999480 (1999-12-01), Ong et al.
patent: 6002268 (1999-12-01), Sasaki et al.
patent: 6008679 (1999-12-01), Masuda
patent: 6028458 (2000-02-01), Hamaguchi
patent: 6043118 (2000-03-01), Suwanai et al.
patent: 6043688 (2000-03-01), Shih
patent: 6065141 (2000-05-01), Kitagawa
patent: 6115279 (2000-09-01), Kitsukawa et al.
patent: 6127881 (2000-10-01), Tsay et al.
patent: 6163142 (2000-12-01), Tsujimoto
patent: 6188590 (2001-02-01), Chang et al.
patent: 6198687 (2001-03-01), Sakui et al.
patent: 6288963 (2001-09-01), Kato
patent: 6324088 (2001-11-01), Keeth et al.
patent: 6392928 (2002-05-01), Roohparvar
patent: 6473346 (2002-10-01), Kim et al.
patent: 6556065 (2003-04-01), Keeth et al.
patent: 2002/0008984 (2002-01-01), Keeth et al.
patent: 2005/0091560 (2005-04-01), Beffa
patent: 2007/0127306 (2007-06-01), Sung et al.
patent: 01-008540 (1989-01-01), None
patent: 01184700 (1989-07-01), None
patent: 02054614 (1990-02-01), None
patent: 04-006694 (1992-01-01), None
patent: 07239241 (1995-09-01), None
Yoo, Jei-Hwan et al., “A 32-Bank 1Gb DRAM with 1GB/s Bandwidth,” IEEE International Solid-State Circuits Conference, ISSCC96/Sessions 23/DRAM/Paper SP 23.6, Feb. 1996.
Nitta, Yasuhiko et al., “A 1.6GB/s Data-Rate 1Gb Synchronous DRAM with Hierarchical Square-shaped Memory Block and Distributed Bank Architecture,” IEEE International Solid-State Circuits Conference, ISSCC96/Session 23/DRAM/Paper SP 23.5, Feb. 1996.
JEDEC Solid State Products Engineering Council, “Committee Letter Ballot,” JC-42.3-95-73, Item # 633.13, Apr. 1995.
JEDEC Solid State Products Engineering Council, “Committee Letter Ballott,” JC-42.3-95-72, Item # 633.12, Apr. 1995.
Kitsukawa, Goro et al., “256-Mb DRAM Circuit Technologies for File Applications,” IEEE Journal of Solid-State Circuits, vol. 28, No. 11, Nov. 1993.
Sugibayashi, Tadahiko et al., “A 30-ns 256-Mb DRAM with a Multidivided Array Structure,” IEEE Journal of Solid-State Circuits, vol. 28, No. 11, Nov. 1993.
Taguc
Beffa Raymond J.
Bunker Layne G.
Demer Scott J.
Keeth Brent
Kinsman Larry D.
Lerner David Littenberg Krumholz & Mentlik LLP
Round Rock Research, LLC
Tran Michael T
LandOfFree
256 Meg dynamic random access memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with 256 Meg dynamic random access memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and 256 Meg dynamic random access memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2717624