Static information storage and retrieval – Powering
Reexamination Certificate
2005-02-01
2005-02-01
Tran, M. (Department: 2818)
Static information storage and retrieval
Powering
C365S189090
Reexamination Certificate
active
06850452
ABSTRACT:
A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows in the individual arrays while row decoders are positioned between adjacent columns in the individual arrays. In certain of the gap cells, multiplexers are provided to transfer signals from I/O lines to data lines. A datapath is provided which, in addition to the foregoing, includes array I/O blocks, responsive to the datalines from each quadrant to output data to a data read mux, data buffers, and data driver pads. The write data path includes a data in buffer and data write muxes for providing data to the array I/O blocks. A power bus is provided which minimizes routing of externally supplied voltages, completely rings each of the array blocks, and provides gridded power distribution within each of the array blocks. A plurality of voltage supplies provide the voltages needed in the array and in the peripheral circuits. The power supplies are organized to match their power output to the power demand and to maintain a desired ratio of power production capability and decoupling capacitance. A powerup sequence circuit is provided to control the powerup of the chip. Redundant rows and columns are provided as is the circuitry necessary to logically replace defective rows and columns with operational rows and columns. Circuitry is also provided on chip to support various types of test modes.
REFERENCES:
patent: 4970725 (1990-11-01), McEnroe et al.
patent: 5155704 (1992-10-01), Walther et al.
patent: 5159273 (1992-10-01), Wright et al.
patent: 5212440 (1993-05-01), Waller
patent: 5231605 (1993-07-01), Lee
patent: 5266821 (1993-11-01), Chern et al.
patent: 5373227 (1994-12-01), Keeth
patent: 5379263 (1995-01-01), Ogawa et al.
patent: 5481179 (1996-01-01), Keeth
patent: 5519360 (1996-05-01), Keeth
patent: 5526364 (1996-06-01), Roohparvar
patent: 5552739 (1996-09-01), Keeth et al.
patent: 5557579 (1996-09-01), Raad et al.
patent: 5574697 (1996-11-01), Manning
patent: 5614859 (1997-03-01), Ong
patent: 5627716 (1997-05-01), Lagree et al.
patent: 5651011 (1997-07-01), Keeth
patent: 5677645 (1997-10-01), Merritt
patent: 5838627 (1998-11-01), Tomishima et al.
patent: 5960455 (1999-09-01), Bauman
patent: 6043118 (2000-03-01), Suwanai et al.
Sugibayashi et al., “A 30-ns 256-Mb DRAM with a Multidivided Array Structure”, IEEE Journal of Solid-State Circuits, vol. 28 (No. 11), (Nov. 1993).
Taguchi et al., “A 40-ns 64-Mb DRAM with 64-b Parallel Data Bus Architecture”, IEEE Journal of Solid-State Circuits, vol. 26 (No. 11), (Nov. 1991).
Kitsukawa et al., “256-Mb DRAM Circuit Technologies for File Applications”, IEEE Journal of Solid-State Circuits, vol. 28 (No. 11), (Nov. 1993).
Jedec Solid State Products Engineering Council, “Committee Letter Ballot”, JC-42.3-95-73, Item #633.13, Arlington, VA (Apr. 1995).
Yoo et al., “SP 23.6: A 32-Bank 1Gb DRAM with 1 GB/s Bandwidth”, ISSCC96/Session 23/DRAM/paper SP 23.6.
Nitta et al., “SP 23.5: A 1.6GB/s Data-Rate 1Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture”, ISSCC96/Session 23/DRAM Paper SP 23.5.
U.S. patent application S.N. 08/521,583, entitled Improved Voltage Regulator Circuit, filed Aug. 30, 1995.
U.S. patent application S.N. 08/668,347, entitled Differential Voltage Regulator, filed Jun. 26, 1996.
U.S. patent application S.N. 08/460,234, entitled Single Deposition Layer Metal Dynamic Random Access Memory, filed Aug. 17, 1995.
U.S. patent application S.N. 08/420,943, entitled Dynamic Random-Access Memory, filed Jun. 4, 1995.
U.S. patent application S.N. 08/194,184, entitled Integrated Circuit Power Supply Having Piecewise Linearity, filed Feb. 8, 1994.
U.S. patent application S.N. 08/137,679, entitled A Voltage Reference Circuit with Common Gate Loading for a Current Mirror Output Stage, fled Oct. 14, 1993.
U.S. patent application S.N. 08/325,766, entitled an Efficient Method for Obtaining Usable Parts from a Partially Good Memory Integrated Circuit, fled Oct. 19, 1994.
Bunker Layne G.
Keeth Brent
Micro)n Technology, Inc.
Thorp Reed & Armstrong LLP
Tran M.
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