2's complement floating-point multiply accumulate unit

Details 2's complement floating-point multiply accumulate unit 2's complement floating-point multiply accumulate unit

1996-04-04

1999-04-06

Mai, Tan V.

Boots, shoes, and leggings

G06F 738

Patent

active

058926984

ABSTRACT:
A fully 2's complement FMAC (floating-point multiply accumulate unit) produces an unrounded output. The unrounded output is associated with a single INC bit, and is provided for early delivery as an FMAC operand. The INC bit is set using rounding logic which anticipates how a 2's complement conversion will affect a number, and then sets the INC bit in response to a rounding mode, and current L, G, S and sign bits. The rounding logic is configured to implement a truth table which demonstrates that rounding and 2's complement incrementation are mutually exclusive. When a bypassed result is received as an input to an FMAC, a delayed incrementer merges the unrounded C operand with its INC bit. The C incrementer and additional 2's complement conversion logic are placed approximately parallel with the multiply unit so that no additional delay is incurred in the FMAC's critical path. An INC bit corresponding to an A or B operand is absorbed within the FMAC's multiply unit. The FMAC allows an entire adder to be eliminated since the (A*B) result and C operand may be added in a single 2's complement adder rather than two carry propagate adders coupled to an end-around carry MUX.

REFERENCES:
patent: 4969118 (1990-11-01), Montoye et al.
patent: 5530663 (1996-06-01), Garcia et al.
Design of the IBM RISC System/6000 floating-point execution unit by R. Montoye, E. Hokenek and S.L. Runyon IBM J. Res. Develop. vol. 34 No. 1 Jan. 1990.
IEEE Standard for Binary Floating-Point Arithmetic Published by The Institute of Electrical and Electronics Engineers, Inc. Aug. 12, 1985.

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