Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression
Reexamination Certificate
1998-12-15
2001-07-31
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Unwanted signal suppression
C327S558000, C327S336000, C327S103000, C327S355000, C330S306000
Reexamination Certificate
active
06268765
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an integrated circuit and more particularly to an integrated circuit with a continuous-time filter and variable gain amplifier.
BACKGROUND OF THE INVENTION
Present computer systems typically use hard-disk drive systems for mass storage. An exemplary hard disk drive read channel of the prior art is shown at
FIG. 1. A
magnetic surface of the hard disk
101
induces electrical signals in the read head
103
. The data rate of these signals varies with each zone of the hard disk drive. These read signals are amplified by preamplifier circuit
105
and applied to variable gain amplifier
109
and programmable analog filter
111
of the read channel analog front end
107
. The programmable filter performs anti-aliasing and channel equalization for analog-to-digital (ADC) circuit
113
. This ADC circuit subsequently produces digital signals suitable for digital processor
115
.
Conventional design techniques may not be adequate for state-of-the-art read channel applications for several reasons. First, a native tolerance of resistor-capacitor (RC) products is typically ±40%. Such variation is incompatible with a required filter group delay accuracy of ±5% at a high corner frequency of 100 MHz. Second, variable gain amplifier (VGA) gain and bandwidth requirements for conventional techniques may require a relatively large unity-gain bandwidth of 5.85 GHz. Finally, conventional attempts to avoid gain-bandwidth limitations may result in an increase in power dissipation.
SUMMARY OF THE INVENTION
These problems are resolved by a circuit comprising a first transconductor circuit with a first input terminal coupled to receive a voltage signal, a second input terminal coupled to receive a control signal and an output terminal. The first transconductor circuit has a gain responsive to the control signal. A first integrator circuit has an input terminal coupled to the first transconductor circuit output terminal and an output terminal. A second transconductor circuit has an input terminal coupled to the first integrator circuit output terminal and an output terminal. A second integrator circuit has an input terminal coupled to the second transconductor circuit output terminal and has an output terminal.
The present invention avoids conventional gain-bandwidth limitations by incorporating a variable gain amplifier within a cascade filter.
REFERENCES:
patent: 5491604 (1996-02-01), Nguyen et al.
patent: 5508570 (1996-04-01), Laber et al.
patent: 5625317 (1997-04-01), Deveirman
“A 4-MHz CMOS Continuous-Time Filter with On-Chip Automatic Tuning”, Krummenacher, et. al.,IEEE Journal of Solid-State Circuits, vol. 23, No. 3, Jun. 1988, pp. 750-758.
“A 20-MHz Sixth-Order BiCMOS Parasite-Insensitive Continuous-Time Filter and Second-Order Equalizer Optimized for Disk-Drive Read Channels”, Laber, et. al.,IEEE Journal of Solid-State Circuit, vol. 28, No. 4, Apr. 1993, pp. 462-470.
“A 20MHz 6thOrder BiCMOS Programmable Filter Using Parasitic-Insensitive Integrators”, Laber, et. al., Digest of Technical Papers, Int. Symp. On VLSI Circuits, Paper 7-D.3, pp. 104-105, 1992.
An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors, Jim Dunning, et. al.,IEEE Journal of Solid-State Circuits, vol. 30, No. 4, Apr. 1995, pp. 412-422.
“Design Considerations for High-Frequency Continuous-Time Filters and Implementation of an Antialiasing Filter for Digital Video”, Gopinathan, et. al.,IEEE Journal of Solid-State Circuits, vol. 25, No. 6, Dec. 1990, pp. 1368-1378.
“Fully Differential Operational Amplifiers with Accurate Output Balancing”, Banu, et. al.,IEEE Journal of Solid-State Circuits, vol. 23, No. 6, Dec. 1988, pp. 1410-1414.
“Good-bye PRML, hello DFE: Adaptive read channel debuts”, Dakshinamurthy, et. al., Electronics, Data Storage, Mar. 1996, 4 pages.
“Monolithic 10-30 MHz Tunable Bipolar Bessel Lowpass Filter”, Vierman, et. al., IEEE Proc. ISCAS, Paper 7-D.2, pp. 521-524.
Choi Davy H.
Gopinathan Venugopal
Tarsia Maurice
Le Dinh T.
Rountree Robert N.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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