Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control
Reexamination Certificate
2002-05-17
2003-09-02
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Frequency or repetition rate conversion or control
C327S117000, C327S202000, C327S219000, C377S047000, C377S048000
Reexamination Certificate
active
06614274
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates in general to a full-speed divider, and, more particularly, to a 2/3 full-speed divider which operates at high frequency range and low power consumption, usable in dual modulus prescaler.
2. Description of the Related Art
Phase locked loop (PLL) frequency synthesizers are widely used in various communications systems and micro-processors. Phase locked loop digital frequency synthesizers are used in radio frequency receivers and transmitters to generate a signal whose frequency is precisely controlled. A variable frequency oscillator is controlled with a feedback system consisting of a variable modulus prescaler driven by the oscillator, which in turn drives a programmable digital divider. The output of the programmable digital divider is compared in a phase detector with the output of a reference oscillator and (in some cases) a reference frequency digital divider. The output of the phase detector is filtered to provide the frequency control signal for the oscillator, typically a voltage applied to a diode to control its capacitance. The diode is resonated with an inductor, forming a tuned circuit which controls the frequency of the variable frequency oscillator. The frequency of the synthesizer is changed by changing the effective divide ratio between the variable frequency oscillator and the phase detector, controlled by the modulus of the prescaler and the modulus of the programmable divider. The filter must perform two functions; first, to remove high frequency components of the phase detection process and second, to stabilize the control loop. These requirements are often in conflict. Unwanted spectral components from the filter frequency modulate the variable oscillator, resulting in spurious modulation sidebands which limit the usefulness of the synthesizer system. Controlling these unwanted signal components by lowering the cutoff frequency of the filter reduces the tuning speed.
The 2/3 (or 4/5) full-speed divider is the most crucial block in the high speed dual modulus prescaler. A conventional prescaler is limited to operating at the maximum frequency which consumes a lot of power. Moreover the operating frequency is limited by the operating speed of the prescaler. The performance of conventional dividers is fast enough for high speed and frequency operations. As a result, there is a need for a full-speed divider which operates low power consumption and at high speed.
SUMMARY OF INVENTION
It is an object of the present invention to provide a full-speed divider that can operate at high speed with low power consumption.
A D flip-flop can be implemented using different technologies depending on the application. The present invention provides a divider comprising a D flip-flop that is suitable for very high frequency applications such as in prescalers used in PLL loops. It is common to use an ECL D flip-flop because it gives the best performance in term of product vs. delay characteristics. The ECL logic is a non saturating high speed logic and is commonly used in applications where high speed is more important than current consumption.
In accordance to the preferred embodiment of the present invention, the 2/3 full-speed divider operating at high speed with low power consumption comprising a ECL D flip-flop in master-slave configuration and a phase-selection block is provided. The master latch and slave latch comprise a pair of input terminals, a pair of control terminals, and a pair of output terminals. The master latch further comprises two pairs of complementary cross-couple transistors for amplifying the output of the master latch for entering the phase-selection block. The phase-selection block has a pair of input terminals, a clock signal input terminal, and an output terminal generating an output signal adjusted by a division ratio according to the clock signal. The division ratio is either 1/2 or 1/3 and the divider functions as a 2/3 divider.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4777388 (1988-10-01), Widener
patent: 5801565 (1998-09-01), Kuo
patent: 5859890 (1999-01-01), Shurboff et al.
patent: 6157693 (2000-12-01), Jayaraman
patent: 6191629 (2001-02-01), Bisanti et al.
Chi Baoyong
Shi Bingxue
Callahan Timothy P.
Jiang Chyun IP Office
Luu An T.
Winbond Electronics Corp.
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