1X asynchronous data sampling clock for plus minus topology appl

Pulse or digital communications – Repeaters – Testing

Patent

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Details

375106, 327291, H04L 2700

Patent

active

053655478

ABSTRACT:
The present invention relates to a system for asynchronous transmission and reception of data between control units. The system includes a first control unit which is operatively connected to a first asynchronous transmitter-receiver circuit, a second control unit operatively connected to a second asynchronous transmitter-receiver circuit and a single media connected between the first and second control units, which facilitates serial communication of data therebetween. Each asynchronous transmitter receiver circuit includes a transmitter portion having circuit for separately processing odd data bits and even data bits at a rate between 1 MHz and 40 MHz, and a receiver portion for processing received data signals and extracting the odd and even data bits therefrom. The receiver portion has a data sampling clock circuit which includes a received data-to-clock position circuit for determining the position of the received data signals, and circuit for determining a true center of the received data signals and for selecting a proper sampling clock for the received data signals. The system also includes an interface portion for serially transmitting the odd and even data bits on a single media in response to the transmitter portion and for receiving serial data from the single media and detecting positive and negative transitions of the received data signals.

REFERENCES:
patent: 4118686 (1978-10-01), Lender
patent: 4481640 (1984-11-01), Chow et al.
patent: 4539533 (1985-09-01), French

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