17-bit cascadable comparator using generic array logic

Communications: electrical – Digital comparator systems

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E06F 702

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active

050235907

ABSTRACT:
A cascadable seventeen-bit self-testing comparator (20) is produced on a twenty-four pin GAL.RTM. 39V18 generic array logic chip by so interconnecting the data pins (1-17) with the logic macro cells (24a-h, 26a-i), and configuring the macro cells, that any data applied to the pins is registered in the macro cells (24a-h, 26a-i) upon pulsing the clock (35), and any exact coincidence of subsequent data with the registered data causes one of the macro cells (26j) to generate a match-indicating output (61).

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patent: 4760374 (1988-07-01), Moller

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