16B/20B encoder

Details 16B/20B encoder 16B/20B encoder

1996-03-28

1997-09-02

DeBoer, Todd

Coded data generation or conversion

Digital code to digital code converters

To or from run length limited codes

341106, H03M 700

Patent

active

056637241

ABSTRACT:
A 16-bit data block is partitioned into upper 5-bit and 3-bit sub-blocks and lower 5-bit and 3-bit sub-blocks. During a single clock cycle, a first 5B/6B encoder portion encodes the upper 5-bit sub-block to produce an upper 6-bit sub-block, a first 3B/4B encoder portion encodes the upper 3-bit sub-block to produce an upper 4-bit sub-block, a second 5B/6B encoder portion encodes the lower 5-bit sub-block to produce a lower 6-bit sub-block, and a second 3B/4B encoder portion encodes the lower 3-bit sub-block to produce a lower 4-bit sub-block. During the same clock cycle, the running disparities of the upper 6-bit sub-block, the upper 4-bit sub-block and the lower 6-bit sub-block are simultaneously combinationally passed to the first 3B/4B encoder portion, the second 5B/6B encoder portion and the second 3B/4B encoder portion, respectively, to selectively complement the output sub-block to adjust running disparity. During the next clock cycle, the running disparity of the lower 4-bit sub-block is passed to the first 5B/6B encoder for the same purpose.

REFERENCES:
patent: 4486739 (1984-12-01), Franaszek et al.
patent: 5177482 (1993-01-01), Cideciyan et al.

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