1000base-t packetized trellis coder

Details 1000base-t packetized trellis coder 1000base-t packetized trellis coder

1997-08-28

1999-03-09

Moise, Emmanuel L.

Excavating

375262, 375265, G06F 1110, H03M 1312

Patent

active

058810749

ABSTRACT:
A packetized trellis coder and method is disclosed for providing error correction coding of IEEE 802.3 frame formatted Ethernet packets for transmission at one gigabit per second (Gbps) over twisted-pair wiring has been disclosed. The error correction code protects each byte of the ethernet frame with a parity bit constructed using a convolutional encoder such that a maximum likelihood sequence estimation at the receiver using a Viterbi decoder will result in a significant receiver performance gain. At the end of the Ethernet packet, the trellis coder restores the states of the convolutional encoder to a known value (state 0) before beginning Idle transmission so that the Viterbi decoder at the receiver can read off the end-of-packet symbols without any performance penalty. The mapping and the inverse mapping from raw data bits to symbols and vice-versa can be implemented with simple gates due to algorithmic symbol mapping of a 4-D trellis code via 1-D partitioning. The same redundancy that is needed for control code transmission in Ethernet frames is used to achieve the trellis coding and to improve receiver performance.

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