10 Gbit/sec transmit structure with programmable clock delays

Details 10 Gbit/sec transmit structure with programmable clock delays 10 Gbit/sec transmit structure with programmable clock delays

2007-01-02

2007-01-02

Vanderpuye, Kenneth (Department: 2613)

Optical communications

Transmitter and receiver system

Including synchronization

C398S154000

Reexamination Certificate

active

10256821

ABSTRACT:
The present invention provides a robust solution to the task of re-aligning data at the transmit end of a fiber optic or other high performance serial link, and also offers flexibility in the circuit board design approach. A high performance analog phase locked-loop circuit is used to simultaneously provide clock recovery for multiple bit streams. The power dissipation required to perform clock recovery is thereby reduced to a fraction of that required in conventional transmit systems. This analog phase locked loop produces plural phase output signals. An output multiplexer selects one phase for use in electrical to optical conversion.

REFERENCES:
patent: 5946456 (1999-08-01), Nakamura
patent: 6044122 (2000-03-01), Ellersick et al.
patent: 6166572 (2000-12-01), Yamaoka
patent: 6188692 (2001-02-01), Huscroft et al.
patent: 6704908 (2004-03-01), Horan et al.
patent: 6728492 (2004-04-01), Baroncelli
patent: 2002/0105386 (2002-08-01), Shastri
patent: 2003/0038681 (2003-02-01), Djafari et al.

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