Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-03-28
2004-03-23
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185300, C365S218000
Reexamination Certificate
active
06711065
ABSTRACT:
BACKGROUND OF THE INVENTION
The threshold voltage of flash memory cells often changes when the cell is electrically erased. Flash memory cells have floating gates that selectively store charge to program the cell on or off (“1” or “0”). Erasing charge on a floating gate can continue beyond a neutral level to place a net positive charge on the floating gate. That results in a low threshold voltage, or in extreme cases, a net negative threshold voltage. A low or negative threshold voltage can electrically short out a bitline of memory or increase leakage current of the same bitline. That will cause false readings of logic “1s” ones from the column during a read operation even if the selected cell is in a logic “0” state. Over-erased cells with low threshold draw high current. That is a problem for low power, portable electronic devices, such as personal digital assistants, cell phones and laptop computers. When their EEPEOM memories arrays are in a low power mode, the draw from over erased cells is large and causes false readings. In addition, the threshold voltage of the cell may change after electrical erasure due to coupling ratio and tunneling probability yielding a much wider threshold voltage distribution.
Conventional flash memories have addressed this problem using several techniques. For instance, see the verified-erase method of V. N. Kyunett et al., “A 90-ns One-Million Erase/Program Cycle 1-Mbit Flash Memory,” IEEE J. Solid-State Circuits, vol. SC-24, no. 10, pp. 1238-1243, 1989. It pre-programs cells and provides a complicated erase algorithm when repeated cell programming results in leaky cells. However, the distribution of threshold voltages of all cells in a memory is usually Gaussian and ranges typically from 4 volts down to 0 volts. Such devices rely upon reiterative erasure until a cell is erased to a desired discharge level. Consequently, the time required to erase a bit vary greatly among the cells.
Reducing the spread of the distribution of threshold voltages (Vt) provides a more overall uniform erase threshold voltage. There are two step erase procedures that shrink the spread of the erased Vt distribution. With these two step procedures, flash EEPROM array is erased and its threshold voltage distribution of the erased flash EEPROM cells is converged to within a predetermined voltage range. In the first step, a conventional “edge” or “channel” electrical bulk erase procedure is accomplished by applying a high voltage to the source (edge erase) or the control gate (channel erase) of the cell. Erase occurs according to a Fowler-Nordheim tunneling mechanism that causes electrons to tunnel from the floating gate to the source (edge erase) or body (channel erase), resulting in cells with a relatively low threshold voltage. In the second step, the cell is programmed by applying a high voltage to the control gate (using Fowler-Nordheim tunneling) to converge the erased threshold voltage distribution of the array to within the predetermined voltage range. The drain, source and substrate of the 1T flash transistor are grounded or presented with no bias across those regions. This grounded or non-biasing approach allows chip-wise or block-wise memory recovery from over erasure, but no bitline-wise recovery. Another method is the self-convergence erasing scheme that typically uses channel hot carrier injection. (see S. Yamada et al., “A Self-Convergence Erasing Scheme for a Simple Stacked gate Flash EEPROM,” IEEE IEDM Tech. Dig., pp. 307-310, 1991 and K. Yoshikawa et al., “Comparison of Current Flash EEPROM Erasing Methods: Stability and How to Control,” IEEE IEDM Tech. Dig., p. 595, 1992). However, that method is undesirable due to its high current requirements.
SUMMARY
The invention provides a method for recovering a flash EEPROM cell from over-erasure. In particular it provides a method for recovering cells in an array to converge to a common threshold voltage so that there is no extra leakage due to “low V
t
” cells and no erroneous sensing of data of other cells that share the same bit line during read operations. In its broader aspect, the invention is a method for erasing data stored as charge in programmable cells of an electrically erasable programmable device. The method is performed on an EEPROM cell that comprises a transistor including source, body and drain regions in a substrate with a channel extending between the source and drain region. The source and drain regions have a conductivity opposite the conductivity of the body and the channel. Above the channel is a floating gate and a control gate. The control gate is separated from a floating gate by a dielectric layer. The floating gate is separated from the channel by another dielectric layer. The floating gate stores an electrical charge representative of data.
The erase and recovery method includes a first step of placing a first voltage of one polarity and of a first magnitude level on the control gate of the transistor of the cell. The first voltage is sufficient to erase electrical charge stored in the EEPROM. During erasing, the source and drain regions of the transistor are allowed to float. After erasing, the cell is returned to a common threshold voltage by applying to the control gate a second voltage opposite in polarity to the first voltage and of a second magnitude. Then a third voltage of the first polarity and of a third magnitude, smaller than the second magnitude, is applied to the source and body regions of the transistor. As a result, the EEPROM recovers to near its original threshold voltage. When this method is used on all the cells in an array, each EEPROM cell in the array is returned to near the same threshold voltage.
N-channel devices are recovered by placing a strong positive voltage (about +6 volts) on the control gate, lowering the voltage on drain (bit line) and the body to about −3 volts and letting the source float. P-channel devices are recovered in the opposite manner. After erasure, a strong negative voltage (about −6 volts) is applied to the control gate, the voltage on the drain (bit line) and the body are raised to about +3 volts and the source is allowed to float. The currents required to recover the cells to their desired erased state are lower than the currents required by other methods. In addition, the array can be erased by cell, row or column depending upon the array structure.
REFERENCES:
patent: 5838618 (1998-11-01), Lee et al.
patent: 5862078 (1999-01-01), Yeh et al.
patent: 5903499 (1999-05-01), Peng et al.
patent: 5949717 (1999-09-01), Ho et al.
patent: 6049484 (2000-04-01), Lee et al.
patent: 6055183 (2000-04-01), Ho et al.
patent: 6411547 (2002-06-01), Choi
patent: 6525970 (2003-02-01), Wang et al.
Kynett, Virgil Niles, et al, “A90-ns One-Million Erase/Program Cycle 1-Mbit Flash Memory”,IEEE Journal of Solid-State Circuits, vol. 24, No. 5, pp. 1259-1264, (Oct. 1989).
Yamada, Seiji, et al., “A Self-Convergence Erasing Scheme For a Simple Stacked Gate Flash EEPROM”,IEEE, vol. 91, pp. 307-310, (1991).
Yoshikawa, Kuniyoshi, et al., “Comparison of Current Flash EEPROM Erasing Methods: Stability and How to Control”,IEEE, vol. 92, pp. 595-598 (1992).
Ludwig Christoph
Shum Danny
Tempel George
FitzGerald Esq. Thomas R.
Infineon - Technologies AG
Nguyen Viet Q.
LandOfFree
1 T flash memory recovery scheme for over-erasure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with 1 T flash memory recovery scheme for over-erasure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and 1 T flash memory recovery scheme for over-erasure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3221684