1-out-of-N decoder circuit

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Reexamination Certificate

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C365S230050, C365S189020

Reexamination Certificate

active

06466510

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a decoder circuit for driving a selected instance from a set of N output lines on the basis of an M-bit address and in response to a turn-on signal. The decoder circuit of this type includes: a number K≧2 of parallel input decoders, each of which receives an associated segment of the M-bit address and, for each bit pattern to be expected for this segment, activates precisely one instance of its outputs which is uniquely associated with this bit pattern; an output decoder which contains, for each of the N output lines, a separate drive path having a plurality of controllable switches whose switching paths are arranged in series between the output line in question and a drive potential; a coupling network for coupling each of the N different subsets of the input decoder outputs, which respectively contain one output of each of the K input decoders, to the control connections of K instances of the controllable switches in one instance of the N drive paths which is associated with the subset in question, such that these switches turn on when those instances of the input decoder outputs which are coupled to them have been activated.
The drive paths are connected through only during the appearance of a turn-on signal.
Such 1-out-of-N decoders are known in general and they are conventionally used to address row and column selection lines on a matrix of memory cells. This is also the preferred field of application of the present invention.
If the number N of output lines to be selectively driven is relatively high, such as in the case of addressing in a memory matrix, the 1-out-of-N decoding is usually performed in sub steps. In this context, the M-bit address is split into K segments, where the number m
k
of bits in the individual segments may be the same or different. For the K address segments, a group of K parallel 1-out-of-m
k
input decoders is used, each of which receives the bits of a segment associated with it and, for each bit pattern to be expected for this segment, activates precisely one instance of its m
k
outputs which is associated with this bit pattern. Hence, in the full set of all the input decoder outputs, only a subset is ever activated, which comprises precisely K outputs, a respective one from each input decoder. In total, there are N such subsets, corresponding to the N possible bit combinations which can be expected in the M-bit address for addressing the N output lines. The M-bit address received on the input decoders thus determines which of the subsets of input decoder outputs is activated.
For further decoding of the address and for driving the respectively addressed output line, each of the N subsets of the input decoder outputs mentioned is connected to K control inputs of an individually associated combinational logic circuit in an output decoder. Accordingly, the output decoder contains N such combinational logic circuits, a respective one for each of the N output lines. In known address decoders, as are customary in connection with memory matrices, for example, each of these combinational logic circuits comprises a drive path containing K+1 switches in series. This drive path is arranged between the output line in question and a potential source supplying the electric “drive potential” to which the output lines are to be connected in the driven state. The control connections of K instances of these switches in each drive path form the control inputs connected to the K associated input decoder outputs. Each of these K switches is connected (i.e. on) only when the input decoder output connected to its control connection has been activated. The control connection of the (K+1)th switch is connected for receiving the turn-on signal; this switch is on only during the active state of the turn-on signal.
In some applications of a multistage 1-out-of-N decoder system containing K input decoders and an output decoder, only limited space is available for each of the N drive paths in the output decoder. This is true particularly if the system is used as an address decoder for selecting word lines or word line groups or else bit lines in a memory matrix and is integrated on the same chip as the matrix. In this case, for layout reasons, it is usually imperative for the individual drive paths of the output decoder, e.g. for the word lines, to be arranged such that their longitudinal extent firstly runs transversely with respect to the direction of the word lines and secondly does not exceed a particular measure. This measure depends on the distance between the individual word lines and on how many word lines are associated with each of the N output lines or with each of the drive paths of the output decoder. The closer the word lines are arranged next to one another, the less space is ultimately available for the longitudinal extent of a drive path. This space has to accommodate the series of switches contained in the drive path.
This space requirement creates problems, particularly when, as is usual, the K+1 switches in each drive path are in the form of field effect transistors (FETs), in particular MOS-type transistors (MOSFETs), whose channels form the switching paths and whose gates form the control electrodes. For a field effect transistor to turn off reliably, the channel between the source and the drain needs to have a certain minimum length. This sets a lower limit for the total length of the drive path and hence a lower limit for the distance between the word lines. This, of course, conflicts with the desire for increasing miniaturization of memory chips.
It is therefore desirable to optimize the field effect transistors used in this context such that the ratio of their channel length to their total dimension is as high as possible. It is known that, during photolithographic fabrication of field effect transistors, there is a tendency for the charge carriers implanted in the source and drain zones after they have been formed to diffuse into the adjacent region of the channel zone during subsequent high-temperature processing steps, and hence to reduce the effective length of the channel. This disadvantageous effect can be eliminated by following application of the gate oxide with implantation of charge carriers of opposite conduction type into the border regions between the channel on the one hand and the source and drain on the other. Since these boundary regions are covered by the gate oxide, they can only be hit if implantation is carried out from a very oblique direction under the lateral edge of the gate oxide. This measure is known as “halo implantation” and is also customary when fabricating switching transistors for the drive paths in the output decoder of word line addressing circuits.
On an integrated series circuit having a plurality of field effect transistors, optimizing halo implantation can be performed effectively only if the transistors are at a certain minimum distance from one another. This is because, with a very close arrangement, the gaps between the gate oxide regions of adjacent transistors are too narrow to allow unimpeded oblique irradiation of the implant material under the lateral edges of the gate oxide. The desired and inherently advantageous halo implantation thus sets a new limit for miniaturization.
The problems described above are just a few of the more prevalent and important examples of the drawbacks of the prior art multistage 1-out-of-N decoder circuits.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a decoder circuit, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which is designed such that the space required for the drive paths in the output decoder can be used more advantageously than previously. It is a particular object of the invention to allow the interspace between the switches in each drive path to be made larger than previously without needing to increase the size of the space for the total length of the driv

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