1/N-rate encoder circuit topology

Details 1/N-rate encoder circuit topology 1/N-rate encoder circuit topology

2006-06-06

2006-06-06

Jeanglaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from nrz codes

C341S158000, C375S281000

Reexamination Certificate

active

07057538

ABSTRACT:
An encoder circuit and a related method for its operation, in which digital encoding, such as differential phase-shift keyed (DPSK) encoding, is performed as a parallel operation on N bits at a time. Each encoded bit is both output in parallel with the others of the N bits and is coupled as an input to encode the immediately next bit in the input data stream. The Nthencoded bit is fed back to the first encoder stage for use in encoding the (N+1)thbit in the input stream. The encoder typically includes a serial-to-parallel converter at the encoder inputs, and a parallel-to-serial converter at the encoder outputs.

REFERENCES:
patent: 4611196 (1986-09-01), Fernandez
patent: 5222103 (1993-06-01), Gross
patent: 6151336 (2000-11-01), Cheng et al.
patent: 6826371 (2004-11-01), Bauch et al.

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