1-bit adder and multiplier containing a 1-bit adder

Details 1-bit adder and multiplier containing a 1-bit adder 1-bit adder and multiplier containing a 1-bit adder

1994-06-20

1996-05-07

Envall, Jr., Roy N.

Boots, shoes, and leggings

364759, G06F 752

Patent

active

055153097

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND

E.g. for video applications fast digital multipliers with high resolution are required. But a higher resolution results in more partial products to be calculated internally. The Booth-Mc Sorley algorithm can be used in order to reduce the required number of such partial products. This algorithm is disclosed in O. L. MAC SORLEY, `High-Speed Arithmetic in Binary Computers`, Proceedings of the IRE, January 1961, Vol. 49, Pages 67-91. This algorithm can be combined with a diagonal propagation of the carry from one partial product to the other, allowing all the sums on a line to be calculated simultaneously. But the reachable multiplication time is not short enough.


INVENTION

It is one object of the invention to disclose a 1-bit adder with improved speed. This object is reached by the inventive adder disclosed in claim 1.
In principle the inventive adder comprises a carry stage and an adding stage and is constructed in a fast CMOS complementary pass transistor logic with complementary analogue CMOS switches in said adding stage which consist of a PMOS and a NMOS transistor, whereby the source of said PMOS transistor is connected with the drain of said NMOS transistor and the drain of said PMOS transistor is connected with the source of said NMOS transistor and the gate of said PMOS transistor receives inverted signals with respect to the gate of said NMOS transistor, and whereby two partial output sum signals are generated by two of said switches which are connected with the input and with the output, respectively, of an inverter and the output sum signal of said adder is available at the output of said inverter.
Advantageous additional embodiments of the inventive adder are resulting from the respective dependent claim.
It is a further object of the invention to disclose a digital multiplier with improved speed which utilizes the inventive adder. This object is reached by the inventive multiplier disclosed in claim 3.
In principle the inventive multiplier uses Booth encoding of the multiplicator and diagonal propagation of the carry from one partial product to the other and comprises: multiplicand and from a substring of the multiplicator which has been coded in a Booth encoder circuit; blocks and one of said 1-bit adders and which calculate further partial products from the partial products from the previous row and from further substrings of the multiplicator, which have been coded in further Booth encoder circuits, whereby the respective two or more lowest multiplication result bits from each row are calculated using two of said 1-bit adders and whereby groups of such rows are connected by a pipeline row; 4- and/or 3-bit adder circuit and/or pairs of said 4- and/or 3-bit adder circuits, which contain said 1-bit adders.
Advantageous additional embodiments of the inventive multiplier are resulting from the respective dependent claims.
Extensive electrical simulations have shown that with 1.2.mu. CMOS technology (HF3CMOS) a multiplication time of 9 ns cannot be achieved in one step. Such a short multiplication time would normally need submicron MOS technology or the use of ECL techniques.
Several levels of pipeline are required within the inventive multiplier. Taking into account the delay of the input and output latches, the multiplier has an overall latency of 5 (i.e. 45 ns for a 108 MHz clock). For reducing the multiplication time within subblocks of the multiplier a carry select technique is used to have minimum propagation delay. For this reason, too, an inventive 1-bit full adder has been designed which uses complementary pass transistor logic. This adder has the advantage of giving full power supply swings at the outputs whilst still maintaining the speed properties of the pass transistor logic.


DRAWINGS

Preferred embodiments of the invention will now be described with reference to the accompanying drawings, in which:
FIG. 1 shows a known n*n bit parallel multiplier;
FIG. 2 shows an element in the partial product generator of the known multiplier;
FIG. 3 shows an overall block diagram

REFERENCES:
patent: 5151875 (1992-09-01), Sato
patent: 5235537 (1993-08-01), McWhirter et al.
patent: 5291431 (1994-03-01), Ho et al.
IEEE International Solid State Circuits Conference, vol. 37, 15 Feb. 1990, New York US pp. 114-115, Yoshino et al "A 100 MHZ 64-Tap FIR Digital Filter in a 0.8 .mu.m BiCMOS Gate Array".
Computer, vol. 11, No. 10 Oct. 1978, Long Beach US, pp. 19-29, Waser, "High-Speed Monolithic Multipliers for Real-Time Digital Signal Processing".
Journal of VLSI Signal Processing, vol. 2, No. 4, May 1991, Dordrecht NL, pp. 219-233, North et al. ".beta.-bit Serial/Parallel Multipliers".
IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, Oct. 1982 New York US, pp. 898-907, Ware et al, "64 Bit Monolithic Floating Point Processors" .

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