0-100% duty cycle, transformer isolated FET driver

Details 0-100% duty cycle, transformer isolated FET driver 0-100% duty cycle, transformer isolated FET driver

1991-06-24

1992-12-01

Howell, Janice A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307261, 307269, H03K 17687, H03K 501, H03K 513

Patent

active

051681820

ABSTRACT:
A transformer isolates a control circuit from a FET, the control circuit including a clock generator for providing, when enabled, a clock signal to the transformer primary. A PWM input selectively disables the clock generator from providing the clock signal to the transformer primary. The transformer secondary is connected in a full wave centertap configuration for providing a full wave rectified version of the clock signal, the full wave rectified version being a relatively constant DC voltage signal supplied at one level to the FET to turn on the FET when the clock generator is enabled to provide the clock signal to the primary. The centertap configuration provides a relatively constant DC voltage signal at a second level to the FET to turn off the FET when the clock generator is disabled by the PWM input from providing the clock signal to the primary.

REFERENCES:
patent: 4201928 (1980-05-01), Koetsch
patent: 4471422 (1984-09-01), Hierholzer, Jr.
patent: 4634903 (1987-01-01), Montorfano
patent: 4709161 (1987-11-01), Mizohata et al.

Affiliated with

Also associated with

Rating

0-100% duty cycle, transformer isolated FET driver does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with 0-100% duty cycle, transformer isolated FET driver, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and 0-100% duty cycle, transformer isolated FET driver will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-504454