Synchronous type semiconductor memory device

Details Synchronous type semiconductor memory device Synchronous type semiconductor memory device

1999-02-05

2000-04-25

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36518904, 36518907, 365194, G11C 800

Patent

active

060552107

ABSTRACT:
When the frequency of an external clock signal is higher than a prescribed frequency in an SDRAM, an output signal from a clock frequency detection circuit is at an L level, a transfer control signal is fixed to an H level, and first and second data buses are coupled together. Thus, a malfunction when the transfer control signal attains an H level in a pulse manner while read data is not output to the first data bus can be prevented. Accordingly, an SDRAM having a larger operating frequency range can be obtained.

REFERENCES:
patent: 5740123 (1998-04-01), Uchida
patent: 5764584 (1998-06-01), Fukiage et al.
patent: 5768177 (1998-06-01), Sakuragi
patent: 5903514 (1999-05-01), Sawada

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