Method of making multilayered interconnects using hillock studs

Details Method of making multilayered interconnects using hillock studs Method of making multilayered interconnects using hillock studs

1986-06-03

1988-03-01

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437189, 437195, 437196, 437200, 437201, H01L 2128, H01L 21302

Patent

active

047286270

ABSTRACT:
A method of manufacturing a semiconductor device comprising the steps of preparing a semiconductor substrate on which a first insulation film is formed, forming a first conductive layer on the first insulation film, forming a hillock of the first conductive layer, forming a second insulation film on the structure, removing that portion of the second insulation film, in self-align with the hillock, which is on the hillock, thereby forming a contact hole leading to the first conductive layer, and forming on the structure a second conductive layer extending into the contact hole and contacting the first conductive layer.

REFERENCES:
patent: 4462149 (1984-07-01), Schwabe
Japanese Patent Disclosure (Kokai) No. 59-107539; N. Ohwada et al. disclosed on Jun. 21, 1984.
Japanese Patent Disclosure (Kokai) No. 60-105255, Y. Takamatsu et al. disclosed on Jun. 10, 1985.
Japanese Patent Disclosure (Kokai) No. 60-147137, Z. Morichika disclosed on Aug. 3, 1985.
Ghandhi, S. K. "VLSI Fabrication Principles", 1983, pp. 446-449.

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