Fishing – trapping – and vermin destroying
Patent
1986-03-18
1988-03-01
Ozaki, George T.
Fishing, trapping, and vermin destroying
437200, 437228, H01L 21425
Patent
active
047286202
DESCRIPTION:
BRIEF SUMMARY
The present invention relates to a process for the production of a MIS-type integrated circuit (metal-insulator semiconductor) and more particularly of the MOS or CMOS type. It more particularly applies in the field of electronics and information processing to the production of logic gates, flip-flops, read-only or read/write memories, etc.
Integrated circuits and more particularly MOS or CMOS circuits are fundamentally formed from n and/or p channel transistors, which are electrically interconnected. In integrated circuits, there are several conductor layers located at different levels ensuring the interconnection of the transistors of these circuits. The formation of these different connection levels makes it necessary to have a very planar circuit structure.
The stages of the processes for the production of integrated circuits used for obtaining relatively planar structures are generally known as planarization stages.
Unfortunately the use of such a technology in existing integrated circuit production processes leads to serious difficulties during contacting of sources and drains of the transistors forming these circuits. This disadvantage is illustrated by the attached FIG. 1, which is a diagrammatic longitudinal section of part of a prior art MOS integrated circuit.
FIG. 1 shows a MOS-type transistor 2, produced on a semiconductor substrate 4, particularly of monocrystalline silicon. Transistor 2 has a source 6 and a drain 8, produced by ion implantation in substrate 4, as well as a gate 10, generally made from polycrystalline silicon, surmounting a gate oxide 12 positioned above substrate 4 between source 6 and drain 8. The active zone of said transistor 2 is surmounted by an insulating layer 14, generally made from silicon dioxide and serving interalia to insulate gate 10 from the source 6 and drain 8 of said transistor. In said insulating layer 14 are formed electrical contact holes 16, 18, respectively, permitting the electrical contacting with the transistor source 6 and drain 8.
This transistor 2 is electrically insulated from the other components and particularly the other transistors constituting the integrated circuit by silicon dioxide zones 20, which are partly buried in the substrate and constituting what is called the field oxide of the circuit. On said field oxide is generally produced a first interconnection level 22 permitting the interconnection of part of the transistors of the integrated circuit. The oxide layer 14, in which are formed the contact holes 16 and 18 of the source and drain also permits an electrical insulation between the first interconnection level 22 of the integrated circuit and the following level.
In order to ensure a good electrical insulation between the first interconnection level 22 and the next level, it is necessary for the insulating layer 14 to have, between said first interconnection level and the next level, a minimum height h, which is typically approximately 0.7 .mu.m. Bearing in mind the thickness of the field oxide 20 (close to 0.5 .mu.m) and the first interconnection line 22, said minimum height h leads to the production of the electrical contact holes such as 16 and 18 with a relatively large depth H, which is typically approximately 1.4 .mu.m.
The production of relatively deep electrical contact holes causes numerous problems with regard to the contacting of sources and drains, such as the appearance of cracks or breaks in the conductive layer deposited within the contact holes serving to interconnect the sources and/or drains of the transistors and as a result the transistors and integrated circuits produced are defective.
As has been stated hereinbefore, the surface of the integrated circuits must be made as planar as possible during each stage of their production, so as to facilitate the production of the different connections of said circuits.
However, one of the factors prejudicial to the planarity of the integrated circuits is the overlapping of the field oxide thereof by the gate electrode of the components or transistors of said circuits.
REFERENCES:
patent: 4038110 (1977-07-01), Feng
patent: 4135954 (1979-01-01), Chang et al.
patent: 4358891 (1982-11-01), Roesner
patent: 4359816 (1982-11-01), Abbas et al.
patent: 4419813 (1983-12-01), Iwai
patent: 4444605 (1984-04-01), Slawinski
patent: 4506434 (1985-03-01), Ogawa et al.
patent: 4560421 (1985-12-01), Maeda et al.
Commissariat a l''Energie Atomique
Ozaki George T.
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