Structure for sense amplifier arrangement in semiconductor memor

Details Structure for sense amplifier arrangement in semiconductor memor Structure for sense amplifier arrangement in semiconductor memor

1989-12-05

1991-10-15

Clawson, Jr., Joseph E.

Static information storage and retrieval

Format or disposition of elements

365 63, 365154, 365190, 365208, 357 68, G11C 506

Patent

active

050580582

ABSTRACT:
A plurality of sense amplifiers (SAj), each of which is connected with each bit line pair extending from a memory cell array region of a dynamic random access memory for sensing and amplifying voltage difference between the bit line pair, are arranged along the longitudinal direction of the bit line pairs. Each bit line pair is formed by a first bit line (BLj) and a second bit line (BLj). A plurality of memory cells (Mij) are arranged on intersection points between some of the bit lines (BLj, BLj) and word lines (WLi), thereby to form the memory cell array region. At least the first bit line (BLj) or the second bit line (BLj) forming each bit line pair connected to each sense amplifier (SAj) is adapted to intersect with other sense amplifier(s) (SAj) provided on the memory cell array region side as viewed from each sense amplifier (SAj). The sense amplifiers can be arranged independently of the spaces between the bit lines. The sense amplifier circuit having desired characteristics can be structured, while the density of the memory cell array can be increased.

REFERENCES:
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patent: 4596001 (1986-06-01), Baba
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LSI Technology & Application, by Ohm-Sha, "A Separate Volume of `Electronics` March", Mar. 5, 1986, pp. 21-26.
NTT articles, Matsumura et al., "Pseudo Folded Bit Line Structure", pp. 498, 499.

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