Computer system with high speed data transfer capabilities

Details Computer system with high speed data transfer capabilities Computer system with high speed data transfer capabilities

1988-09-09

1991-10-15

Hecker, Stuart N.

Boots, shoes, and leggings

364244, 364246, 3642463, 364254, 3642543, G06F 1300

Patent

active

050580051

ABSTRACT:
The present invention is a computer system which can perform master unit controlled memory accesses at a first rate, DMA controlled operations at a second rate and burst operations of both types at a higher third rate. The burst operation is set up by performing a standard access cycle, thus setting up the dynamic random access memory row address, and then performing a series of fast, column address-only accesses to the same page of memory. The fast mode must be exited to a standard rate access whenever a page boundary is crossed, with burst operations recommencing thereafter. Wait states can be inserted in all type operations. Timing diagrams and controller state machines are disclosed.

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