Self-aligned semiconductor devices

Details Self-aligned semiconductor devices Self-aligned semiconductor devices

1989-05-11

1991-10-15

Larkins, William D.

357 239, 357 2311, 357 59, H01L 2704

Patent

active

050579029

ABSTRACT:
A novel process is provided for fabricating transistors (14), contacts (46s, 40g, 46d) and interconnections (46c) in a novel self-aligned configuration. The process of the invention permits higher packing densities, and allows feature distances to approach 0.5 .mu.m and lower. In a preferred embodiment, the configuration is also planarized. A unique combination of masks in conjunction with a multi-layer structure (28) formed on the surface of a semiconductor wafer (16), the multi-layer structure including a buried etch-stop layer therein (28b), defined the source (18), gate (22), and drain (20) elements and their geometry relative to each to each and to interconnects. Polysilicon plug (40, 46) contacts through slots in the multi-structure layer permit vertical contact to be made to the various elements. Silicidation (56) of the polysilicon plugs reduces series resistance in the vertical direction and permits strapping of N.sup.+ and P.sup.+ polysilicon plugs.

REFERENCES:
patent: 4016587 (1977-04-01), de la Moneda
patent: 4306915 (1981-12-01), Shiba
patent: 4374700 (1983-02-01), Scott et al.
patent: 4450470 (1984-05-01), Shiba
patent: 4543592 (1985-09-01), Itsumi et al.

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