Power conservation in synchronous SRAM cache memory blocks of a

Details Power conservation in synchronous SRAM cache memory blocks of a Power conservation in synchronous SRAM cache memory blocks of a

1995-07-14

1998-05-12

Harvey, Jack B.

Boots, shoes, and leggings

364707, G06F 132

Patent

active

057520453

ABSTRACT:
A synchronous cache memory power conservation apparatus for conserving power of the cache SRAM memory blocks in cached computer systems. The power conservation apparatus is included as a portion of the logic of the cache controller of the computer system. The power conservation apparatus monitors the CPU bus cycles in order to shut off the clocking signals supplied to the cache SRAM memory blocks when the CPU is not accessing the cache memory, thereby reducing the power consumption of the high-power SRAM devices. The power conservation apparatus resumes standard synchronized clocking to the cache SRAM blocks when the CPU is performing a cache-hit memory access cycle for maximum cache access performance.

REFERENCES:
patent: 5018061 (1991-05-01), Kishigami et al.
patent: 5452401 (1995-09-01), Lin
patent: 5530932 (1996-06-01), Carmean et al.
patent: 5539681 (1996-07-01), Alexander et al.

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