Fault tolerant processing section with dynamically reconfigurabl

Details Fault tolerant processing section with dynamically reconfigurabl Fault tolerant processing section with dynamically reconfigurabl

1992-05-13

1995-06-06

Beausoliel, Jr., Robert W.

G06F 1108

Patent

active

054230241

ABSTRACT:
A fault-tolerant digital data processor includes three identical logic CPU boards connected to a voting bus and a system bus. The three boards are initially designated as a master board, a slave board 0 and a slave board 1. The master board drives the system bus and the two slave boards serve as backups in case the master breaks. The master board issues signals, at different instances with the aid of multiplexing, to the slave boards. On the slave boards, corresponding signals are compared and the result is broadcast to all three boards. When all three boards are compared equal, the master board remains as master. If there is a miscompare between one slave board and the master but not between the other slave board and the master, the master board remains master, and the slave board with which the miscompare occurred will be disabled after another miscompare. If a miscompare occurs between the master board and both slave boards, a re-execution of the previous cycle occurs. After a master board failure is confirmed, a slave board becomes a master board, and if there is another comparison failure the former master board is disabled.

REFERENCES:
patent: 3460094 (1969-08-01), Pryor
patent: 3593307 (1971-07-01), Gouge
patent: 3665173 (1972-05-01), Bouricius et al.
patent: 3681578 (1972-08-01), Stevens
patent: 3783250 (1974-01-01), Fletcher
patent: 4412281 (1983-10-01), Works
patent: 4521745 (1985-06-01), Falconer
patent: 4562575 (1985-12-01), Townsend
patent: 4583224 (1986-04-01), Ishii
patent: 4610013 (1986-09-01), Long
patent: 4622667 (1986-11-01), Yount
patent: 4654846 (1987-03-01), Goodwin et al.
patent: 4739498 (1988-04-01), Eichhorn
patent: 4799140 (1989-01-01), Dietz
patent: 4907232 (1990-03-01), Harper et al.
patent: 5195040 (1993-03-01), Goldsmith
Publication Extract entitled "Design Techniques to Achieve Fault Tolerance".
Yoichi Yano et al, "V60/V70 Microprocessor and its Systems Support Functions", Digest of Papers of the Spring Compcon '88, Feb. 28, 1988, San Francisco, Calif., pp. 36-42.
N. Prawitz, "Deux Microprocesseurs A Unites Specialisees--LES V60 ET V70", Electronique Industrielles, No. 13, Jun. 1987, Paris, FR, pp. 48-53.
R. Evers et al., "88K Fault Tolerance and Testability", Electronics Test, vol. 13, No. 4, Apr. 1990, San Francisco, Calif., pp. 51-57.

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