Method and apparatus for simultaneously executing instructions i

Details Method and apparatus for simultaneously executing instructions i Method and apparatus for simultaneously executing instructions i

1997-09-03

1998-05-12

Treat, William M.

395394, G06F 938

Patent

active

057519846

ABSTRACT:
An instruction combination unit for a microprocessor compares multiple fetched instructions to determine whether they can be combined for simultaneous execution. The instruction combination unit compares destination registers of preceding instructions against source registers of subsequent instructions. If a subsequent instruction is to operate on a result of a preceding instruction before the result of the preceding instruction is available to the subsequent instruction, a data access conflict arises. The instructions are compared, and combined, if possible. Otherwise, execution of the subsequent instruction is stalled until the result from the preceding instruction is available to the subsequent instruction.

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Kenji Minagawa, et al., "Pre-Decoding Mechanism for Superscalar Computers," IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, May 9-10, 1991.
Peter M. Kogge, The Architecture of Pipelined Computers, McGraw-Hill Book Company, Hemisphere Publishing Corporation, pp. 95-99 and pp. 107-112.
Jean-Loup Baer, Computer Systems Architecture, Computer Science Press, Inc., pp. 135-215.

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