Out-of-order processor with a memory subsystem which handles spe

Details Out-of-order processor with a memory subsystem which handles spe Out-of-order processor with a memory subsystem which handles spe

1995-10-03

1998-05-12

Lim, Krisna

395393, G06F 338

Patent

active

057519838

ABSTRACT:
A method and apparatus for speculatively dispatching and/or executing LOADs in a computer system includes a memory subsystem of a out-of-order processor that handles LOAD and STORE operations by dispatching them to respective LOAD and STORE buffers in the memory subsystem. When a LOAD is subsequently dispatched for execution, the store buffer is searched for STOREs having unknown addresses. If any STOREs are found which are older than the dispatched LOAD, and which have an unknown address, the LOAD is tagged with an unknown STORE address identification (USAID). When a STORE is dispatched for execution, the LOAD buffer is searched for loads that have been denoted as mis-speculated loads. Mis-speculated loads are prevented from corrupting the architectural state of the machine with invalid data.

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