Preserving the zero mark for wafer alignment

Details Preserving the zero mark for wafer alignment Preserving the zero mark for wafer alignment

1999-02-11

2000-04-25

Tsai, Jey

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

438692, H01L 2176

Patent

active

060543612

ABSTRACT:
A method of preserving alignment marks through steps of depositing intermetal dielectric, depositing refractory metal, and planarizing the wafer is described. After deposition of a layer of first metal a layer of first intermetal dielectric is deposited on an integrated circuit wafer. The first intermetal dielectric is then etched away from the alignment region of the wafer. A layer of second metal is then deposited. A layer of second intermetal dielectric is then deposited. The layer of second intermetal dielectric is left in place in the alignment region, a layer of refractory metal is deposited, and the wafer is planarized. The refractory metal and second intermetal dielectric are then cleared from the alignment region. The second intermetal dielectric protects the alignment marks during wafer planarization. A layer of third metal can then be deposited and the alignment marks are be preserved.

REFERENCES:
patent: 5270255 (1993-12-01), Wong
patent: 5271798 (1993-12-01), Sandhu et al.
patent: 5316966 (1994-05-01), Van Der Plas et al.
patent: 5496777 (1996-03-01), Moriyama
patent: 5532520 (1996-07-01), Haraguchi et al.
patent: 5627624 (1997-05-01), Yim et al.
patent: 5640053 (1997-06-01), Caldwell
patent: 5705320 (1998-01-01), Hsu et al.
patent: 5733801 (1998-03-01), Gojohbori

Affiliated with

Also associated with

Rating

Preserving the zero mark for wafer alignment does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Preserving the zero mark for wafer alignment, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Preserving the zero mark for wafer alignment will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-992845