Double implanted planar MOS device with V-groove and process of

Details Double implanted planar MOS device with V-groove and process of Double implanted planar MOS device with V-groove and process of

1976-09-30

1978-04-11

Wojciechowicz, Edward J.

357 23, 357 42, H01L 2978, H01L 2702, H01L 2906

Patent

active

040841758

ABSTRACT:
An MOS transistor has a short vertical channel extending along the thickness of the transistor wafer and along the wall of a V-shaped groove, and has laterally disposed source, drain and gate electrodes on the same surface of the wafer. The channel is formed by a double ion implantation, or double diffusion operation. The source and drain electrodes are disposed on the same surface of the wafer and on opposite sides of the V-groove. The transistor has the speed capability of a bipolar transistor and high device density of a silicon gate MOS device, and has a shorter channel length (less than 1 micron) and higher punch-through voltage than has been previously available in a planar-MOS device.

REFERENCES:
patent: 3975752 (1976-08-01), Nicolay

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