Digital information processing device

Multiplex communications – Channel assignment techniques

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Details

395287, H04L 1228

Patent

active

057517118

ABSTRACT:
In an ATM cell processing device having a data transfer LSI capable of transferring ATM cells, and receiver LSIs capable of receiving the ATM cells having a same content, each data receiver LSI has a data input buffer, a data output buffer connected to the output side of the data input buffer and the input side of the data input buffer is connected to the output side of the data output buffer in the preceding data receiver LSI, and the output side of the data output buffer is connected to the input side of the data input buffer in the following data receiver LSI to form a data transfer path having a cascade connection so that the data of a same content transferred from the data transfer LSI is received in each of the data receiver LSIs in order.

REFERENCES:
patent: 5285444 (1994-02-01), Sakurai et al.
patent: 5404352 (1995-04-01), Pauwels et al.
patent: 5497370 (1996-03-01), Hamada et al.
patent: 5519696 (1996-05-01), Willman et al.
patent: 5566169 (1996-10-01), Rangan et al.

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