Semiconductor integrated circuit device having a hierarchical po

Details Semiconductor integrated circuit device having a hierarchical po Semiconductor integrated circuit device having a hierarchical po

1995-10-23

1998-05-12

Nguyen, Viet Q.

Static information storage and retrieval

Powering

326121, 326 83, 326 17, 326 33, H03K 190948

Patent

active

057516510

ABSTRACT:
A main source voltage transmission line for transmitting a source voltage VCH as one power source and a sub source voltage transmission line are provided corresponding to a gate circuit. A resistive element having a high resistance is provided between the main source voltage transmission line and the sub source voltage transmission line. A capacitor comprised of an insulated gate field effect transistor is connected to the sub source voltage transmission line. The gate circuit is operated with a voltage on the sub source voltage transmission line as an operating source voltage. Thus, the voltage on the sub source voltage transmission line can be maintained at a voltage level that balances with a sub-threshold current flowing through the gate circuit, and the voltage on the sub source line can be stably maintained by the capacitor. A semiconductor memory device can be realized which reduces the sub-threshold current that flows upon standby of the gate circuit and minimizes a difference in voltage between the sub source voltage transmission line and the main source voltage transmission line to operate at high speed with low current consumption.

REFERENCES:
patent: 5521527 (1996-05-01), Sakata et al.
patent: 5583457 (1996-12-01), Horiguchi et al.
"256Mb DRAM Technologies for File Application", Kitsukawa et al., IEEE International Solid-State Circuits Conference, Feb. 24, 1993, pp. 48-49.
"Subthreshold-Current Reduction Circuits For Multi-Gigabit DRAM's", Sakata et al, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, May 19-21, 1993, pp. 45-46.

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